In this paper we investigate possible ways to improve the energy efficiency of a general purpose microprocessor. We show that the energy of a processor depends on its performance, so we chose the energy-delay product to compare different processors. To improve the energy-delay product we explore methods of reducing energy consumption that do not lead to performance loss (i.e. wasted energy), and explore methods to reduce delay by exploiting instruction level parallelism. We found that careful design reduced the energy dissipation by almost 25%. Pipelining can give approximately a 2/spl times/ improvement in energy-delay product. Superscalar issue, however, does not improve the energy-delay product any further since the overhead required offsets the gains in performance. Further improvements will be hard to come by since a large fraction of the energy (50-80%) is dissipated in the clock network and the on-chip memories. Thus, the efficiency of processors will depend more on the technology being used and the algorithm chosen by the programmer than the micro-architecture.

Energy dissipation in general purpose microprocessors

A 28 mW/MHz at 80 MHz structured-custom RISC microprocessor design is described. This 32-b implementation of the PowerPC architecture is fabricated in a 3.3 V, 0.5 /spl mu/m, 4-level metal CMOS technology, resulting in 1.6 million transistors in a 7.4 mm by 11.5 mm chip size. Dual 8-kilobyte instruction and data caches coupled to a high performance 32/64-b system bus and separate execution units (float, integer, loadstore, and system units) result in peak instruction rates of three instructions per clock cycle. Low-power design techniques are used throughout the entire design, including dynamically powered down execution units. Typical power dissipation is kept under 2.2 W at 80 MHz. Three distinct levels of software-programmable, static, low-power operation-for system power management are offered, resulting in standby power dissipation from 2 mW to 350 mW. CPU to bus clock ratios of 1/spl times/, 2/spl times/, 3/spl times/, and 4/spl times/ are implemented to allow control of system power while maintaining processor performance. As a result, workstation level performance is packed into a low-power, low-cost design ideal for notebooks and desktop computers. >

A 2.2 W, 80 MHz superscalar RISC microprocessor

Portable devices demand low power consumption to prolong battery life. Gating the clock is one strategy for saving power. The authors' technique identifies self-loops in an FSM and uses the function described by the self-loops to gate the clock. Applying these techniques to standard benchmarks achieved an average 25% less power dissipation at a cost of only 5% more area. >

Saving power by synthesizing gated clocks for sequential circuits

Somerset Design Center he 604 microprocessor is the third member of the PowerPC family being developed jointly by Apple, IBM, and Motorola. Developed for use in desktop personal computers, workstations, and servers, this 32-bit implementation works with the software and bus in the PowerPC 601 and 603 microprocessors.‘m3 While keeping the system interface compatible with the 601 microprocessor, we improved upon it by incorporating a phase-locked loop and an IEEE-Std 1149.1 boundary-scan QTAG) interface on chip. In addition, an advanced machine organization delivers one and a half to two times the 601’s integer performance.

The PowerPC 604 RISC microprocessor.

This paper contains an evaluation of trends in the key system parameters (e.g., size, weight, function, performance, battery life) for battery-powered portable computers, together with a review of development trends in the technologies required for such systems. The discussion focuses on notebook-size portable computers. Those technologies which will have substantial impact on battery life and power budgets of future notebook computers receive the primary emphasis in this paper for example, liquid crystal displays, storage technology, wireless communication technology, and low power electronics. System power management is also be addressed. The basic theme of this paper is first to develop a view of what the key attributes of future notebook computers will be, and then to discuss how technologies must evolve to allow such systems to be advanced over the current state of the art in terms of portability and battery life. >

Technology directions for portable computers

The PowerPC 603 microprocessor is the second member of the PowerPC microprocessor family. The 603 is a superscalar implementation featuring low power operation of less than 3 watts while maintaining high performance of 75 SPECint92 (estimated) at 80 MHz. The 7.4 mm by 11.5 mm design is implemented in 0.5 /spl mu/m, four-level metal CMOS technology. The 603 features dual 8-kByte instruction and data caches and a 32/64-bit system bus. Peak instruction rates of 3 instructions per clock cycle give outstanding performance to notebook and portable applications. >

The PowerPC 603 microprocessor: a high performance, low power, superscalar RISC microprocessor

This superscalar microprocessor is a 32b implementation of the PowerPC Architecture. With an estimated performance/power ratio of 25SPECint92/W at 80 MHz, this RISC style chip offers workstation-level performance packed into a low-power consumption, low-cost design ideal for notebooks and desktop computers. >

http://ieeexplore.ieee.org/iel2/1111/8026/00344665.pdf

S.P. Litch

Papers

The PowerPC 603 microprocessor: a high performance, low power, superscalar RISC microprocessor

A 3.0 W 75SPECint92 85SPECfp92 superscalar RISC microprocessor