Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components. DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off (or reducing the performance of) system components when they are idle (or partially unexploited). In this paper, we survey several approaches to system-level dynamic power management. We first describe how systems employ power-manageable components and how the use of dynamic reconfiguration can impact the overall power consumption. We then analyze DPM implementation issues in electronic systems, and we survey recent initiatives in standardizing the hardware/software interface to enable software-controlled power management of hardware components.

A survey of design techniques for system-level dynamic power management : Special section on low-power electronics and design

Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off (or reducing the performance of) system components when they are idle (or partially unexploited) In this paper, we survey several approaches to system-level dynamic power management We first describe how systems employ power-manageable components and how the use of dynamic reconfiguration can impact the overall power consumption We then analyze DPM implementation issues in electronic systems, and we survey recent initiatives in standardizing the hardware/software interface to enable software-controlled power management of hardware components

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A survey of design techniques for system-level dynamic power management

In this paper we investigate possible ways to improve the energy efficiency of a general purpose microprocessor. We show that the energy of a processor depends on its performance, so we chose the energy-delay product to compare different processors. To improve the energy-delay product we explore methods of reducing energy consumption that do not lead to performance loss (i.e. wasted energy), and explore methods to reduce delay by exploiting instruction level parallelism. We found that careful design reduced the energy dissipation by almost 25%. Pipelining can give approximately a 2/spl times/ improvement in energy-delay product. Superscalar issue, however, does not improve the energy-delay product any further since the overhead required offsets the gains in performance. Further improvements will be hard to come by since a large fraction of the energy (50-80%) is dissipated in the clock network and the on-chip memories. Thus, the efficiency of processors will depend more on the technology being used and the algorithm chosen by the programmer than the micro-architecture.

Energy dissipation in general purpose microprocessors

Processors used in portable systems must provide highly energy-efficient operation, due to the importance of battery weight and size, without compromising high performance when the user requires it. The user-dependent modes of operation of a processor in portable systems are described and separate metrics for energy efficiency for each of them are found to be required. A variety of well known low-power techniques are re-evaluated against these metrics and in some cases are not found to be appropriate leading to a set of energy-efficient design principles. Also, the importance of idle energy reduction and the joint optimization of hardware and software will be examined for achieving the ultimate in low-energy, high-performance design.

Processor design for portable systems

Dynamic power management schemes (also called policies) reduce the power consumption of complex electronic systems by trading off performance for power in a controlled fashion, taking system workload into account. In a power-managed system it is possible to set components into different states, each characterized by performance and power consumption levels. The main function of a power management policy is to decide when to perform component state transitions and which transition should be performed, depending on system history, workload, and performance constraints. In the past, power management policies have been formulated heuristically. The main contribution of this paper is to introduce a finite-state, abstract system model for power-managed systems based on Markov decision processes. Under this model, the problem of finding policies that optimally tradeoff performance for power can be cast as a stochastic optimization problem and solved exactly and efficiently. The applicability and generality of the approach are assessed by formulating the Markov model and optimizing power management policies for several systems.

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Policy optimization for dynamic power management

The PowerPC 603 incorporates a variety of features to reduce power dissipation: dynamic idle-time shutdown of separate execution units, low-power cache design, and power considerations for standard cells, data-path elements, and clocking. System-level features include three software-programmable static power management modes and a hardware-programmable phase-lock loop. Operating at 80 MHz, the 603 typically dissipates 2.2 W, while achieving an estimated 75 Specint92 and 85 Specfp92. >

PowerPC 603, a microprocessor for portable computers

The PowerPC 603 microprocessor is a low-power implementation of the PowerPC architecture The superscalar organization includes dynamic localized shutdown of execution units to reduce normal-mode power consumption Three levels of static low-power operation are software programmable for system power management The 603 PLL (phase lock loop) is capable of generating an internal processor clock at 1/spl times/, 2/spl times/, 3/spl times/ or 4/spl times/ the system clock speed to allow control of system power while maintaining processor performance Various design features optimize the 603 for both power and performance, creating an ideal microprocessor solution for portable applications >

The PowerPC 603 microprocessor: a low-power design for portable applications

This superscalar microprocessor is a 32b implementation of the PowerPC Architecture. With an estimated performance/power ratio of 25SPECint92/W at 80 MHz, this RISC style chip offers workstation-level performance packed into a low-power consumption, low-cost design ideal for notebooks and desktop computers. >

http://ieeexplore.ieee.org/iel2/1111/8026/00344665.pdf

H. Sanchez

Papers

PowerPC 603, a microprocessor for portable computers

The PowerPC 603 microprocessor: a low-power design for portable applications

A 3.0 W 75SPECint92 85SPECfp92 superscalar RISC microprocessor