Showing papers by "Saeid Nooshabadi published in 2010"

Design of a Tunable All-Digital UWB Pulse Generator CMOS Chip for Wireless Endoscope

Abstract: A novel tunable all-digital, ultrawideband pulse generator (PG) has been implemented in a standard 0.18-? m complementary metal-oxide semiconductor (CMOS) process for implantable medical applications. The chip shows that an ultra-low dynamic energy consumption of 27 pJ per pulse without static current flow at a 200-MHz pulse repetition frequency (PRF) with a 1.8-V power supply and low area of 90 × 50 ?m2. The PG generates tunable pulsewidth, amplitude, and transmit (Tx) power by using simple circuitry, through precise timing control of the H-bridge output stage. The all-digital architecture allows easy integration into a standard CMOS process, thus making it the most suitable candidate for in-vivo biotelemetry applications.

MBMS raptor codes design trade-offs for IPTV

Abstract: Raptor codes bring significant improvement to the performance of the forward error correction (FEC) scheme for 3rd Generation Partnership Program (3GPP) Multimedia Broadcast/Multicast Services (MBMS). They have become an integrated part of the fast growing mobile consumer services and technologies - the multimedia content broadcast and delivery. In this work, we analyze the trade-offs involved in the implementation of systems employing MBMS. We show the performance for various packet erasure rates with fixed and variable Raptor code symbol overhead. We analyze the quality of service, for different block and symbol sizes and system throughputs. With the rise of new highly attractive but computationally intensive services, the lack of either the performance or the power in the mobile devices becomes a serious issue. We investigate the limiting effects of the Raptor decoder complexity on the performance of the mobile receiver system. Finally, we identify the system parameters that trade-off the Raptor coding performance for the decoding complexity.

Strategies for the design of raptor decoding in broadcast/multicast delivery systems

Abstract: In this paper we analyze the decoding performance of Raptor codes in Broadcast/Multicast delivery systems. Based on the extensive analysis of the statistics of the behavior of the Raptor codes, we introduce an efficient decoding strategy targeting real time applications on embedded systems. Further, we propose a new efficient incremental decoding algorithm. We show that the proposed algorithm performs up to 42% better than the existing algorithm, when implemented in software on an embedded system platform. We also show that when implemented on a dedicated hardware, the proposed algorithm is 19 times better than its software version in terms of throughput and energy consumption.

Parallel scalable hardware architecture for hard Raptor decoder

Abstract: In this paper we propose a novel parallel hardware architecture for two binary matrix inversion and vector decoding algorithms, for hard Raptor decoder. We compare the achieved performance to a software based implementation in an embedded processor. We demonstrate the superiority of our proposed architecture in terms of performance (by a factor 12), power and energy dissipation (by a factor of 15). We also include the hardware resource requirements in the comparison. Furthermore, the proposed hardware architecture is parameterized and easily scalable. The data processing word size has been successfully extended up to 1024 bits and fitted within the chosen FPGA hardware platform.

Dual-mode SM/STBC system with antenna subset selection employing ML detection

Abstract: Multiple input multiple output (MIMO) antenna system is a promising candidate to meet the demands of 4th Generation (4G) cellular communication systems by offering increased spectral efficiency through the spatial multiplexing (SM) gain, and improved link reliability through the space–time block coding (STBC) diversity gain. This paper presents a new scheme that combines the dual-mode SM/STBC and the antenna subset selection (AnSS) schemes. In the proposed scheme, the combination of the SM/STBC switching and the full antenna subset selection (AnSS) at both the transmitter (Tx) and the receiver (Rx) ends of the communication channel are adaptively selected through a simple algorithm based on the singular values of the channel matrix at the Rx side. Thus, the new scheme achieves the best BER performance over the previous works regardless of the data rate. The simulation results show that the proposed scheme with the full AnSS outperforms the previous works, by up to the 12.5 dB at the bit error rate (BER) of 10 ‐ 5 . Further, a partial AnSS is also proposed which dramatically reduces both the computational complexity (by 31%) and the hardware (by 50%), cost, without any appreciable loss in the BER performance, when compared with the full AnSS.

Analysis and implementation of Raptor codes on embedded systems

Abstract: Raptor codes have been proven very suitable for mobile multimedia content delivery, and yet they have not been analyzed in the context of embedded systems. At the heart of Raptor codes for binary erasure channel (BEC) is the matrix inversion operation. This paper analyzes the performance, energy profile and resource implication of two matrix inversion algorithms for the Raptor decoder on a system on a chip (SoC) platform with a soft-core embedded processor. We show how the cache size, matrix memory type and organization affect the two algorithms under consideration.

Reduced-complexity orthotope sphere decoding for multiple-input multiple-output antenna system

Abstract: In this paper, we propose a maximum likelihood (ML)-like performance reduced computational complexity sorted orthotope sphere decoding (OSD), and zero forced (ZF) sorted OSD algorithms for the spatial multiplexing (SM) in a multiple-input multiple-output (MIMO) system. In comparison with the original OSD our technique reduces the number of partial Euclidean distance (PED) computations by up to 28%, and 25% for QPSK and 16-QAM 4×4 MIMO systems, respectively.

An energy-efficient successive approximation register analog to digital converter in 180nm

Abstract: This paper presents an analog-to-digital converter using state-of-the-art techniques in 180nm process. Making use of charge sharing, asynchronous logic circuitry, scaled digital voltage supply and a novel sampling scheme, this ADC achieves a figure of merit (FOM) of 45fJ per conversion step in simulations. This FOM is close to reference designs reported in 90nm.

A 200Mbps, 0.66nJ/b DTR UWB receiver for high data rate wireless biotelemetry applications

Abstract: This paper introduces a CMOS design of differential transmit-reference (DTR) ultra-wideband (UWB) receiver in 90nm RF CMOS process for high data rate wireless biotelemetry applications with the operation range of 0.5m and receiver sensitivity of −70dBm. From the simulation results the receiver achieves a data rate of 200Mbps, the highest reported in biotelemetry systems, with a low power consumption of 0.66nJ/bit during the data detection, consuming a small silicon area of 1.17mm2, making it most suitable for the high data rate in-vivo wireless biotelemetry applications.

Low-energy multi-path adiabatic CMOS driver for low-energy system applications with large capacitive load

Abstract: This paper presents the design of a fast multi-path adiabatic CMOS driver (pr-ad). The proposed pr-ad does not uses bootstrap capacitors to minimise active area, and does not require to maintain high voltage difference across the junctions or the gates of output pull-up and output pull-down transistors. When implemented on a 65nm CMOS technology, under the large capacitive loading condition (10pF), pr-ad has a higher active area (33%), but lower energy-delay product (16%) than the reference complementary adiabatic/bootstrap circuit (cab-lwk). Also pr-ad has very small effective input capacitance in comparison with cab-lwk because the first does not need bootstrap capacitors connected with the input.

A genetic algorithm methodology to find the maximum datapath coverage for combinational logic circuits

Abstract: In this paper, we present a genetic algorithm (GA) based methodology for vector generation that maximizes the metric of datapath coverage for a given combinational logic circuit, and compare it wit...

Wireless endoscope system and transceiver method thereof

Abstract: PURPOSE: A wireless endoscope system and a transceiving method thereof are provided to transmit high quality medical images from a capsule endoscope to an external unit by using a UWB(Ultra Wide Band) communications. CONSTITUTION: A first and a second mixing part(821,822) detect the envelop of a UWB image signal which is transmitted from a capsule endoscope. A first and a second low-pass filter(841,842) execute a low-pass filtering process in order to filter the UWB image signal. A first and a second demodulating part(860,870) synthesize the delay signal of the image signal, which is low-pass filtered, with the low-pass filtered image signal. A combining part(880) combines the image signals which are outputted from the first and the second demodulating part.

An adaptive Space-Time Coding / Spatial Multiplexing detector on FPGA

Abstract: This paper presents a novel detector implementation that takes advantage of instantaneous channel states by switching between Space-Time Coding (STC) and Spatial Multiplexing (SM) modes. For a fixed rate, the detector calculates whether the channel is better suited for SM or STC transmission. This decision can then be fed back to the transmitter via a low-rate feedback channel. The detector is designed for a 2 × 2 multiple-input multiple-output (MIMO) system and implemented on an Altera Cyclone II FPGA.

A hybrid equivalent-bit spacing scheme for low energy and high performance for bus signalling

Abstract: Interconnects on deep submicron (DSM) buses incur significantly larger power dissipation, delay performance degradation, and induced signal interference due to coupling capacitance between adjacent wires on the bus. This paper proposes a novel encoding scheme to, further, reduce the coupling energy dissipation, and delay. Further, the energy cost of the overhead encoding scheme in our proposed scheme is significantly reduced. We present an 8-bit to 10-bit equivalent solution that reduces the energy dissipation by 55%, delay by 24%, and energy delay product by 65%, without any additional area penalty on the bus. It also requires much less complex codec circuitry requiring 96% less area overhead, when compared with transition pattern coding (TPC) scheme. Our analysis is based on 65nm CMOS technology.

Application of mixed integer linear programming in the generation of vectors with maximum datapath coverage for combinational logic circuits

Abstract: In this paper, we present a novel methodology for vector generation that maximizes the metric of datapath coverage for a given combinational logic circuit. The proposed methodology is based on Mixed Integer Linear Programming (MILP). The search of input vectors based on the datapath coverage metric is a satisfiability (SAT) problem. In order to obtain maximum coverage vectors, we use a novel model for the Boolean logic gates to translate the original SAT problem into an MILP optimization problem. Next, the new problem is solved following the MILP optimization environment and an exhaustive search strategy. We compare our proposed methodology with the exhaustive search algorithm. Experimental results and performance comparisons based on the large set of MCNC'91 suite of benchmark circuits are presented. They show significant speedups of MILP methodology against the exhaustive search algorithm for the complex circuits.

Power-performance versus algorithmic trade-offs in the implementation of wireless multimedia terminals

Abstract: Circuit design for wireless applications generally involves achieving a certain level of processing speed, dictated by the data transmission rate and algorithmic performance, while minimizing the energy dissipation. This paper discusses some of the circuit techniques that help to achieve this goal. We show that power reduction in a multimedia system involves trade-offs at the algorithmic, algebraic, architectural, and circuit levels of abstraction.