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Saeideh Shirinzadeh

Researcher at University of Bremen

Publications -  31
Citations -  341

Saeideh Shirinzadeh is an academic researcher from University of Bremen. The author has contributed to research in topics: Logic synthesis & In-Memory Processing. The author has an hindex of 9, co-authored 25 publications receiving 251 citations. Previous affiliations of Saeideh Shirinzadeh include University of Gilan.

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Proceedings ArticleDOI

Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs

TL;DR: This paper presents an approach for the synthesis of RRAM-based logic circuits using the recently proposed Majority-Inverter Graphs (MIGs), and proposes a bi-objective algorithm to optimize MIGs with respect to the number of required RRAMs and computational steps in both MAJ-based and IMP-based realizations.
Journal ArticleDOI

Logic Synthesis for RRAM-Based In-Memory Computing

TL;DR: The proposed approach allows to perform parallel computing on a multirow crossbar architecture for the logic representations of the given Boolean functions throughout a level-by-level implementation methodology, and provides alternative implementations utilizing two different logic operations for each representation.
Proceedings ArticleDOI

An MIG-based compiler for programmable logic-in-memory architectures

TL;DR: This work proposes for the first time an automatic compilation methodology suited to a recently proposed computer architecture solely based on resistive memory arrays that uses Majority-Inverter Graphs (MIGs) to manage the computational operations.
Journal ArticleDOI

Time-resolved detection of diffusion limited temperature gradients inside single isolated burning droplets using Rainbow Refractometry

TL;DR: In this paper, the high sensitivity of the rainbow structure to refractive index changes enabled the detection and resolution of time-varying temperature gradients inside combusting droplets.
Proceedings ArticleDOI

Endurance management for resistive Logic-In-Memory computing architectures

TL;DR: This paper monitors the write traffic in a Programmable Logic-in-Memory (PLiM) architecture, and proposes an endurance management scheme for it, capable of handling different trade-offs between write balance, latency, and area of the resulting PLiM implementations.