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Pierre-Emmanuel Gaillardon
Researcher at University of Utah
Publications - 228
Citations - 4535
Pierre-Emmanuel Gaillardon is an academic researcher from University of Utah. The author has contributed to research in topics: Logic gate & Logic synthesis. The author has an hindex of 33, co-authored 213 publications receiving 3424 citations. Previous affiliations of Pierre-Emmanuel Gaillardon include École Polytechnique Fédérale de Lausanne & École Normale Supérieure.
Papers
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Proceedings ArticleDOI
Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs
M. De Marchi,Davide Sacchetto,Stefano Frache,Jian Zhang,Pierre-Emmanuel Gaillardon,Yusuf Leblebici,G. De Micheli +6 more
TL;DR: In this article, two independent gate-all-around electrodes and vertically stacked SiNW channels are used to enable dynamic configuration of the device polarity (n or p-type), while the other switches on/off the device.
The EPFL Combinational Benchmark Suite
TL;DR: The EPFL combinational benchmark suite consists of 23 combinational circuits designed to challenge modern logic optimization tools, available to the public and distributed in all Verilog, VHDL, BLIF and AIGER formats.
Journal ArticleDOI
Majority-Inverter Graph: A New Paradigm for Logic Optimization
TL;DR: This paper proposes a paradigm shift in representing and optimizing logic by using only majority (MAJ) and inversion (INV) functions as basic operations, and develops powerful Boolean methods exploiting global properties of MIGs, such as bit-error masking.
Proceedings ArticleDOI
Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization
TL;DR: This paper introduces a new Boolean algebra, based exclusively on majority and inverter operations, with a complete axiomatic system for efficient optimization of Boolean functions and showcases the MIG potential by proposing a delay-oriented optimization technique.
Journal ArticleDOI
3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS
TL;DR: In this article, the authors report on the main advances enabling the demonstration of functional and performant stacked CMOS-FETs; i.e., wafer bonding, low temperature processes (<;650°C) and salicide stabilization achievements.