S
Santiago Remersaro
Researcher at University of Iowa
Publications - 6
Citations - 358
Santiago Remersaro is an academic researcher from University of Iowa. The author has contributed to research in topics: Automatic test pattern generation & Logic gate. The author has an hindex of 5, co-authored 6 publications receiving 349 citations. Previous affiliations of Santiago Remersaro include Mentor Graphics.
Papers
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Proceedings ArticleDOI
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs
TL;DR: Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests.
Proceedings ArticleDOI
Low Shift and Capture Power Scan Tests
TL;DR: This paper investigates a method to derive tests with reduced switching activity both during scan shifts and during test response captures that does not require additional hardware or modifications to the scan chains.
Proceedings ArticleDOI
ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction
TL;DR: A novel and scalable technique for inserting observation points to aid compression by reducing pattern count and data volume is presented.
Journal ArticleDOI
Scan-Based Tests with Low Switching Activity
TL;DR: This paper proposes a method that fills unspecified entries in test cubes to reduce the switching activity caused by scan tests simultaneously during the scan-shift and capture cycles.
Proceedings ArticleDOI
A scalable method for the generation of small test sets
TL;DR: A scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits and guides the justification and propagation decisions to create patterns that will accommodate most targeted faults.