Showing papers in "IEEE Design & Test of Computers in 2007"
TL;DR: A selection of recently published lightweight-cryptography implementations are presented and compared to state-of-the-art results in their field, targeting embedded hardware and software.
Abstract: The tight cost and implementation constraints of high-volume products, including secure RFID tags and smart cards, require specialized cryptographic implementations. The authors review recent developments in this area for symmetric and asymmetric ciphers, targeting embedded hardware and software. In this article, we present a selection of recently published lightweight-cryptography implementations and compare them to state-of-the-art results in their field.
465 citations
TL;DR: This article reviews efforts to develop various LoC applications using electrowetting-based digital microfluidics, and describes these applications, their implementation, and associated design issues.
Abstract: Digital-microfluidic lab-on-a chip (LoC) technology offers a platform for developing diagnostic applications with the advantages of portability, sample and reagent volume reduction, faster analysis, increased automation, low power consumption, compatibility with mass manufacturing, and high throughput. In addition to diagnostics, digital microfluidics is finding use in airborne chemical detection, DNA sequencing by synthesis, and tissue engineering. In this article, we review efforts to develop various LoC applications using electrowetting-based digital microfluidics. We describe these applications, their implementation, and associated design issues.
365 citations
TL;DR: A pragmatic survey on the state of the art in GALS architectural techniques, design flows, and applications and several industrial inventions and changes in methodology, tools, and design flow that would improve GALS-based integration of IP blocks are provided.
Abstract: This article provides a pragmatic survey on the state of the art in GALS architectural techniques, design flows, and applications. The authors also prescribe several industrial inventions and changes in methodology, tools, and design flow that would improve GALS-based integration of IP blocks.
222 citations
TL;DR: A single-chip secure processor called Aegis incorporates mechanisms to protect the integrity and privacy of applications from physical attacks as well as software attacks, and physically secure systems can be built using this processor.
Abstract: In this article, we introduce a single-chip secure processor called Aegis. In addition to supporting mechanisms to authenticate the platform and software, our processor incorporates mechanisms to protect the integrity and privacy of applications from physical attacks as well as software attacks. Therefore, physically secure systems can be built using this processor. Two key primitives, physical unclonable functions (PUFs) and off-chip memory protection, enable the physical security of our system. These primitives can also be easily applied to other secure computing systems to enhance their security.
219 citations
TL;DR: A GALS approach can facilitate fast block reuse by providing wrapper circuits to handle interblock communication across clock domain boundaries, and may also achieve power savings by clocking different blocks at their minimum speeds.
Abstract: Single-clocked digital systems are largely a thing of the past. Although most digital circuits remain synchronous, many designs feature multiple clock domains, often running at different frequencies. Using an asynchronous interconnect decouples the timing issues for the separate blocks. Systems employing such schemes are called globally asynchronous, locally synchronous (GALS). To minimize time to market, large SoC designs must integrate many functional blocks with minimal design effort. These blocks are usually designed using standard synchronous methods and often have different clocking requirements. A GALS approach can facilitate fast block reuse by providing wrapper circuits to handle interblock communication across clock domain boundaries. SoCs may also achieve power savings by clocking different blocks at their minimum speeds. For example, Scott et al. describe the advantages of GALS design for an embedded-processor peripheral bus.
189 citations
TL;DR: This case study focuses on a massively parallel multiprocessor for real-time simulation of billions of neurons that decouples clocking concerns for different parts of the die, leading to greater power efficiency.
Abstract: This case study focuses on a massively parallel multiprocessor for real-time simulation of billions of neurons. Every node of the design comprises 20 ARM9 cores, a memory interface, a multicast router, and two NoC structures for communicating between internal cores and the environment. The NoCs are asynchronous; the cores and RAM interfaces are synchronous. This GALS approach decouples clocking concerns for different parts of the die, leading to greater power efficiency.
146 citations
TL;DR: An overview of power analysis attacks, which are based on the measurement of the power consumed by cryptographic ICs, and countermeasures against them, andcountermeasures that can be implemented at the cell level are presented.
Abstract: This article focuses on power analysis attacks because they have received by far the most attention in recent years. They are powerful and can be executed relatively easily. This article provides an introduction to these attacks and discusses countermeasures against them. In particular, we focus on countermeasures that can be implemented at the cell level. This article presents an overview of power analysis attacks, which are based on the measurement of the power consumed by cryptographic ICs, and countermeasures against them.
130 citations
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TL;DR: This column looks back at the days when the authors had direct, tactile control of their appliances and wonders what impact the loss of this control is having on their children's interest in engineering.
Abstract: This column looks back at the days when we had direct, tactile control of our appliances and wonders what impact the loss of this control is having on our children's interest in engineering. Increased complexity in our work life also leads to our feeling this lack of direct control. Yet, perhaps it's a mistake to pine for those days of direct control. Maybe our children's ability to find and fix a problem by its symptoms will be essential for testing the products of the future.
129 citations
TL;DR: Two metrics that quantify the impact of power supply noise are described and validates and are emerging as a replacement of SVD analysis for capturing theimpact of power Supply noise on the timing behavior of logic and memory cells.
Abstract: Power integrity is emerging as a major challenge in deep-submicron SoC designs. The lack of predictability is complicating timing closure, physical design, production test, and speed grading of SoCs. This article describes and validates two metrics that quantify the impact of power supply noise. The IC industry is moving quickly to adopt new deep-submicron (DSM) technologies that offer unprecedented integration levels and cost benefits. These advanced technologies pose unexpected challenges to the semiconductor industry. The DSM problems have led the development of SOC design methodologies to deal with the problem of complexity and productivity. To reduce power dissipation, manufacturers have scaled down supply voltage in each successive technology. Designers analyzed power supply noise with static voltage drop (SVD) analysis, which might not reflect the true nature of power supply fluctuations. Dynamic voltage drop (DVD) analysis is emerging as a replacement of SVD analysis for capturing the impact of power supply noise on the timing behavior of logic and memory cells.
112 citations
TL;DR: Here, fault injection methods, types of faults, and fault attack models are surveyed, finding that the protection of fault attacks is more costly in terms of chip area.
Abstract: An active attacker can induce errors during the computation of the cryptographic algorithm and exploit the faulty results to extract information about the secret key in embedded systems. We call this kind of attack a fault attack. Fault attacks can break an unprotected system more quickly than any other kind of side-channel attack such as simple power analysis (SPA), differential power analysis (DPA), or electromagnetic analysis (EMA). For example, the attacker can break RSA-CRT (RSA with Chinese Remainder Theorem) with one faulty result, and Data Encryption Standard (DES) and Advanced Encryption Standard (AES) with two. Furthermore, the protection of fault attacks is more costly in terms of chip area. Here, we survey fault injection methods, types of faults, and fault attack models.
102 citations
TL;DR: Some of the key challenges to successful validation are discussed and why a radical transformation is necessary if validation is to be effective in the near future are shown.
Abstract: Traditionally, universities teach how to make or build things but not so much how to "break" things or find, patch, or prevent breaks. However, much of industry validation hinges on the latter skills. Validation is something that does not get noticed when done well, but everyone notices when something goes wrong - such as the infamous Pentium floating-point division bug. Major semiconductor companies experience postsilicon validation turning into a very expensive, time-consuming proposition, yet very few college graduates are formally trained in the area. Validation is the activity of ensuring a product satisfies its reference specifications, runs with relevant software and hardware, and meets user expectations. Here, I discuss some of the key challenges to successful validation and show why a radical transformation is necessary if validation is to be effective in the near future.
IBM1
TL;DR: The complexity of today's hundreds-of-million-transistor microprocessors all but guarantees imperfect first silicon, but leaves unanswered the question of what exactly will go wrong as mentioned in this paper.
Abstract: The complexity of today's hundreds-of-million-transistor microprocessors all but guarantees imperfect first silicon, but leaves unanswered the question of what exactly will go wrong. This article describes features added to the cell broadband engine processor to enable debugging in the presence of such unknown events.
TL;DR: In this article, analog and digital microelectronic fluidic (MEF) arrays design and testing methods are described for detecting and locating various types of faults in biochips, ranging from electrical defects (shorts, opens, and so on) to material properties, unexpected fluidic flow patterns, and chemical or biological contamination.
Abstract: Biochips can fail because of a wide variety of reasons, ranging from electrical defects (shorts, opens, and so on) to material properties, unexpected fluidic flow patterns, and chemical or biological contamination This article describes the way to detect and locate various types of faults in biochips This article describes analog and digital microelectronic fluidic (MEF) arrays design and testing methods
TL;DR: This article surveys recent advances in hybrid approaches for functional verification that combine multiple verification techniques so that they complement one another, resulting in superior verification effectiveness.
Abstract: This article surveys recent advances in hybrid approaches for functional verification. These approaches combine multiple verification techniques so that they complement one another, resulting in superior verification effectiveness.
TL;DR: This book offers an education in the wide range of areas involved in embedded-systems design, as well as a brief exploration of solutions on the horizon.
Abstract: This is a review of Integrated System-Level Modeling of Network-on-Chip Enabled Multi-processor Platforms (by Tim Kogel, Rainer Leupers, and Heinrich Meyr).This book offers an education in the wide range of areas involved in embedded-systems design, as well as a brief exploration of solutions on the horizon. It should resonate with students, researchers, and practical designers interested in the state of electronic systems-level (ESL) design in 2007.
TL;DR: A low-cost, dual-virtual-CPU hardware technology for embedded-systems security that integrates a rich operating system without requiring significant changes to it, while maintaining preemptive and real-time properties, exception handling, and power management.
Abstract: In this article, we describe a low-cost, dual-virtual-CPU hardware technology for embedded-systems security. We also present a case study of a programmable software design to exploit such hardware. This design integrates a rich operating system without requiring significant changes to it, while maintaining preemptive and real-time properties, exception handling, and power management.
TL;DR: This article investigates the application of different hardware- and software-based approaches to improving on-chip routing elements' dependability, and discusses the advantages and drawbacks of these approaches from an energy consumption perspective.
Abstract: On-chip routing elements are extensively used in complex NoC designs. Faulty operation of such elements due to crosstalk faults or soft errors can severely affect a device's functionality and performance. This article investigates the application of different hardware- and software-based approaches to improving these elements' dependability, and discusses the advantages and drawbacks of these approaches from an energy consumption perspective.
TL;DR: This article shows how to use dielectrophoresis for cell sorting and describes a prototype CMOS chip with a sensor-actuator array, row-column addressing logic and readout circuitry.
Abstract: Precisely manipulating and sorting live cells on a lab on a chip is still a major challenge This article shows how to use dielectrophoresis for cell sorting The authors also describe a prototype CMOS chip with a sensor-actuator array, row-column addressing logic and readout circuitry In this article, we examine the new microelectronic technology that gives scientists the ability to monitor, sort, and analyze vast populations of cells and interact with each cell individually A microelectronic platform called a lab on a chip (LoC) allows precise manipulation of cells with no effect on their phenotypes The motivation for developing this technology is that investigations in recent years have shown that a few cells changing their behavior unexpectedly can induce deadly diseases such as cancer Current LoC design and manufacturing techniques are spawning new biotechnology methods with potential for research, diagnosis, and therapy
TL;DR: The basic principles of some emerging nanoscale technologies are presented, with emphasis on novel devices and their implementation, and manufacturing issues and basic features in terms of performance, current state of development, and limitations are highlighted.
Abstract: Conventional lithography-based vlsi technology (mostly using CMOS) has been extremely successful in the deep-submicron region. As CMOS approaches its fundamental physical limits (as evidenced by ultra thin gate oxides, short channel effects, and so on), researchers have begun investigating new technologies at extremely small feature sizes (such as nanoscale below 45 nm) for manufacturing future electronic and computing systems. This article presents the basic principles of some emerging nanoscale technologies, with emphasis on novel devices and their implementation. We also highlight manufacturing issues and basic features in terms of performance, current state of development, and limitations to present a basic, yet comprehensive, overview of emerging technologies for nanoscale electronics. New devices proposed by researchers include carbon nanotubes, silicon nanowires, quantum-dot cellular automata (QCA), single-electron transistors, resonant tunneling diodes, and single-molecule devices.
TL;DR: The methodology described here employs an on-chip process-monitoring circuit that is easy to integrate on chip and use in a characterization or production environment, to help identify and localize IR-drop hot spots and power-related failures.
Abstract: Many modern designs have large, localized failures due to excessive power consumption, which can be measured as IR drop. The methodology described here employs an on-chip process-monitoring circuit that is easy to integrate on chip and use in a characterization or production environment, to help identify and localize IR-drop hot spots and power-related failures.
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TL;DR: A heuristic method to generate test sequences which create worst-case power drop by accumulating the high-frequency and low-frequency effects by employing a dynamically constrained version of the classical D-algorithm for test generation.
Abstract: High-performance digital ICs manufactured in deep-submicron technologies tend to draw considerable amounts of power during operation. Power droop describes the impact of power consumption transients on the logic values of a circuit's signal lines and, ultimately, on the correctness of the circuit's operation. Although power droop could cause an IC to fail, such failures cannot be screened during testing, because conventional fault models do not cover them. In this article, we present a technique for screening such failures. We propose a heuristic method to generate test sequences that create worst-case power drop by accumulating high- and low-frequency effects. We employ a dynamically constrained version of the classical D-algorithm, which generates new constraints on the fly, for test generation. The obtained patterns can be used for manufacturing test and early silicon validation. We have implemented a prototype ATPG to demonstrate the feasibility of this approach.
TL;DR: It is shown that transient supply noise is sensitive to nonuniform decoupling-capacitor distribution, and that supply-drop locality is a tight function of frequency and package-die resonance, leading to significant localized resonant effects.
Abstract: This article describes a full-die dynamic model of an Intel Pentium IV microprocessor design. The authors show that transient supply noise is sensitive to nonuniform decoupling-capacitor distribution, and that supply-drop locality is a tight function of frequency and package-die resonance, leading to significant localized resonant effects.
TL;DR: Cost and benefit models are presented to evaluate the economic effectiveness of typical memory BISR implementations and show that memory size impacts cost-effectiveness more than production volume does.
Abstract: With the advent of deep-submicron technology and SoC design methodology, it's possible to integrate heterogeneous cores from different sources in a single chip containing millions of gates. The yield of such a large chip is usually too low to be profitable. Therefore, yield enhancement is an important issue in SoC product development. Memory cores usually occupy a large proportion of the area of a typical SoC, and they normally have higher circuit density, so they tend to dominate SoC yield. This article presents cost and benefit models to evaluate the economic effectiveness of typical memory BISR implementations. Experimental results with a simulator based on these cost models show that memory size impacts cost-effectiveness more than production volume does.
TL;DR: In this article, the authors estimate the leakage power of subthreshold, gate-tunneling, and reverse-biased junction band-to-band-tuning (BTBT) currents.
Abstract: Because of the continued scaling of technology and supply-threshold voltage, leakage power has become more significant in power dissipation of nanoscale CMOS circuits. Therefore, estimating the total leakage power is critical to designing low-power digital circuits. In nanometer CMOS circuits, the main leakage components are the subthreshold, gate-tunneling, and reverse-biased junction band-to-band-tunneling (BTBT) leakage currents.
TL;DR: This article discusses several aspects of design and test methodology centered on digital microfluidics, including modeling, simulation, synthesis, test, and reconfiguration, which detects both catastrophic and parametric faults.
Abstract: This article discusses several aspects of design and test methodology centered on digital microfluidics, including modeling, simulation, synthesis, test, and reconfiguration. The automated design methods for digital electronics and adaption of them to droplet-based microfluidics are explained. The test methodology detects both catastrophic and parametric faults by electrically controlling and tracking the motion of the test stimuli droplets and also facilitates concurrent testing, in which fault testing and biomedical assays run simultaneously on a microfluidic system.
TL;DR: This article presents an adaptive solution to latency-insensitive protocols, which the authors show to be more effective than earlier solutions in terms of power, area, and throughput.
Abstract: Latency-insensitive protocols (LIPs) represent a class of interblock protocols designed to overcome long multiclock interconnects. This article presents an adaptive solution to this problem, which the authors show to be more effective than earlier solutions in terms of power, area, and throughput.
TL;DR: Two models for supply noise in delay testing and their application to test compaction are discussed, which avoid complicated power network analysis, making them much faster than existing power noise analysis tools.
Abstract: Excessive power supply noise during test can cause overkill. This article discusses two models for supply noise in delay testing and their application to test compaction. The proposed noise models avoid complicated power network analysis, making them much faster than existing power noise analysis tools. can cause performance degradation and
TL;DR: A methodology for verifying the correctness of RTL refinement from transaction-level modeling guided by an assertion coverage metric on the modules of an industry design is proposed.
Abstract: Transaction-level modeling is an emerging design practice for overcoming increasing design complexity. This article proposes a methodology for verifying the correctness of RTL refinement from transaction-level modeling. The authors demonstrate the effectiveness of this methodology, guided by an assertion coverage metric on the modules of an industry design.
TL;DR: Risin is a redundancy analysis algorithm simulation tool that can calculate an RA algorithm's repair rate, yield, associated memory configuration, and redundancy structure and lets users easily assess and plan redundant elements and subsequently develop BIRA algorithms and circuits, which are essential for BISR of embedded memories.
Abstract: To increase redundancy repair efficiency and thus final yield in embedded- memory cores, we propose Raisin, a redundancy analysis algorithm simulation tool that can calculate an RA algorithm's repair rate, yield, associated memory configuration, and redundancy structure. Raisin lets users easily assess and plan redundant elements and subsequently develop BIRA algorithms and circuits, which are essential for BISR of embedded memories.