International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Reducing size and using of transistors with a vertical gate (FinFET) has led to a significant change and expansion of a set of constructive layout design rules. The three-dimensional structure of the FinFET device and the additional layers appeared between the first metal and the transistor structure changed the parameters of the parasitic elements. Task of extracting parasitic elements in comparison with planar technologies is significantly more complicated. The paper compares two libraries — 7nm FinFET and 28nm planar CMOS to assess of affect new types of parasitic elements. Similar sets of library elements, including “clean” netlists and extracted netlists for each library element, were investigated. The evaluation of the performance degradation was carried out on the standard sets of circuits ISCAS 85/89. The results of the study showed that the average delay degradation is up to 44% for FinFET technology, and up to 37% for CMOS technology.

Comparative analysis of standard cells performance for 7nm FinFET and 28nm CMOS technologies with considering for parasitic elements

Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

Saving and restoring machine state between multiple executions of an instruction

Migration of partially completed instructions. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. The instruction is re-executed on a selected processor to resume forward processing of the instruction. The re-executing includes determining whether model-dependent metadata is to be used by the selected processor in re-executing the instruction. Based on determining the model-dependent metadata is to be used, the model-dependent metadata is used in re-executing the instruction. Based on determining the model-dependent metadata is not to be used, proceeding with re-executing the instruction without using the model-dependent metadata.

Migration of partially completed instructions

The synchronous retention flip-flop circuit comprises a first circuit module suitable for being powered by an interruptible power source and a second circuit module suitable for being powered by a permanent power source. The first circuit module includes first and second latch stages, which are configured to store at least one datum while said interruptible power source is supplying power, transmitting means suitable for being controlled by a second control signal and configured to deliver said at least one datum to the second circuit module before an interruption of said interruptible power source, the second circuit module being configured to preserve said at least one datum during said interruption, and restoring means suitable for being controlled by a first control signal and configured to restore said at least one datum at the end of said interruption. Only the second control signal remains active during interruption of the interruptible power source.

Method for managing the operation of a synchronous retention flip-flop circuit exhibiting an ultra-low leakage current, and corresponding circuit

Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling.

Double sampling state retention flip-flop

In an embodiment, a method for processing instructions in a microcontroller is disclosed. In the embodiment, the method involves, upon receipt of an interrupt while an instruction is being executed, completing execution of the instruction by a shadow functional unit and, upon servicing the interrupt, terminating re-execution of the instruction and updating a main register file with the result of the execution of the instruction by the shadow functional unit.

Method and system for processing interruptible instructions in a microcontroller

In today's semiconductor industry we see a move towards smaller technology feature sizes. These smaller feature sizes pose a problem due to mismatch between identical cells on a single die known as local variation. In this paper a library tuning method is proposed which makes a smart selection of cells in a standard cell library to reduce the design's sensitivity to local variability. This results in a robust IC design with an identifiable behavior towards local variations. Experimental results performed on a widely used microprocessor design synthesized for a high performance timing show that we can achieve a timing spread reduction of 37% at an area increase cost of 7%.

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Standard cell library tuning for variability tolerant designs

A level shifter circuit is described herein for shifting a signal from a first voltage domain to a second voltage domain The level shifter circuit includes two current paths between a supply terminal of the first voltage domain and a supply terminal of the second voltage domain The first and second current paths each include a differential transistor that receives a signal from a pulse generator in a first voltage domain The pulse generator provides pulses to the differential transistors based on an input signal to be translated to the second voltage domain The level shifter includes a latch circuit in the second voltage domain that includes two inputs where each input is biased at a node of one of the current paths Each current path includes a bias transistor whose control terminal receives a compensated biasing voltage for biasing the bias transistor The compensated biasing voltage is compensated to account for drive strength variation of at least one transistor in each current path

Sebastien Antonius Josephus Fabrie

Papers

Double sampling state retention flip-flop

Method and system for processing interruptible instructions in a microcontroller

Standard cell library tuning for variability tolerant designs

Level shifter circuit with transistor drive strength variation compensation

Method and system for processing interrupts with shadow units in a microcontroller