Patent
Double sampling state retention flip-flop
TLDR
A flip-flop circuit includes a master latch, a slave latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling as discussed by the authors.Abstract:
Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling.read more
Citations
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Patent
Method for managing the operation of a synchronous retention flip-flop circuit exhibiting an ultra-low leakage current, and corresponding circuit
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References
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Journal ArticleDOI
Razor: circuit-level correction of timing errors for low-power operation
Daniel J. Ernst,Shidhartha Das,Seokwoo Lee,David Blaauw,Todd Austin,Trevor Mudge,Nam Sung Kim,Krisztian Flautner +7 more
TL;DR: This work presents a DVS approach that uses dynamic detection and correction of circuit timing errors to tune processor supply voltage and eliminate the need for voltage margins.
Proceedings ArticleDOI
TIMBER: time borrowing and error relaying for online timing error resilience
TL;DR: TIMBER, a technique for online timing error resilience that masks timing errors by borrowing time from successive pipeline stages, can recover timing margins without instruction replay or roll-back support.
Proceedings ArticleDOI
Data-retention flip-flops for power-down applications
H. Mahmoodi-Meimand,Kaushik Roy +1 more
TL;DR: A novel technique for retaining data in flip-flops in power-down applications is presented, and a 16-bit shift-register using data-retention flip- flops has been successfully fabricated and tested in a 0.25 /spl mu/m CMOS process.
Patent
Ultra low area overhead retention flip-flop for power-down applications
TL;DR: In this paper, a method and system for data retention is presented, where a data input is latched by a first latch and a second latch coupled to the first latch receives the data input for retention while the first one is inoperative in a standby power mode.
Patent
Power efficient and high performance flip-flop
Joseph Ku,Stuart C. Siu +1 more
TL;DR: In this paper, a power efficient flip-flop includes a power switch regulating power supplied to a high speed latch in the flip flop, and a decoupling device is connected to the power switch to substantially eliminate a coupling effect.