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Shedden Masupe

Researcher at University of Botswana

Publications -  27
Citations -  116

Shedden Masupe is an academic researcher from University of Botswana. The author has contributed to research in topics: Very-large-scale integration & Discrete cosine transform. The author has an hindex of 5, co-authored 27 publications receiving 91 citations. Previous affiliations of Shedden Masupe include Botswana International University of Science and Technology & Cardiff University.

Papers
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Journal ArticleDOI

Analysis of internet of things malware using image texture features and machine learning techniques

TL;DR: Overall, use of texture feature can realize a low computational and platform independent classification scheme for IoT malware.
Journal ArticleDOI

ICT Development in Botswana: Connectivity for Rural Communities

TL;DR: In this paper, the authors highlight the need for rural communities in Botswana to gain access to information and communication technologies (ICTs), and argue that a nascent information society could be upon Botswana, if only the mobile cellular platform and Internet connectivity could be fully harnessed to give people a foothold into the vast ICT field.
Proceedings ArticleDOI

Design and FPGA implementation of digit-serial FIR filters

TL;DR: The design introduces a new digit-serial multiplier that guarantees minimum processing time and reduces the hardware requirements of the filter and allows the use of one common two's complement circuit for all the filter section.
Proceedings ArticleDOI

Low power DCT implementation approach for VLSI DSP processors

TL;DR: An algorithm for the low power implementation of the discrete cosine transform on single multiplier CMOS DSPs reduces power by a combination of using shift operations, where possible, and manipulating bit-correlation between successive cosine coefficients applied to the input of the multiplier section such that the effective switched capacitance is reduced.
Journal ArticleDOI

Low power DCT implementation approach for CMOS-based DSP processors

TL;DR: An algorithm is presented for the low power implementation of the discrete cosine transform on single multiplier CMOS DSPs that reduces power by reducing the amount of switched capacitance within the multiplier section of the DSP.