Sheng-Tsai Wu

TL;DR: In this article, the authors proposed a 3D IC architecture that includes a silicon interposer with Through-Silicon-Vias (TSV) and interconnect wiring layers on both sides of the ILP.

TL;DR: In this article, a system-in-package (SiP) that consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top and bottom sides (a real 3-D IC integration) is studied.

TL;DR: In this article, a single inline Cu-filled TSV with redistribution layer is illustrated and has been used to realize the thermomechanical stress distribution for TSVs in 3D IC integration.

TL;DR: The feasibility of 3D IC integration SiP has been demonstrated in this paper, where a TSV (through-silicon via) interposer with RDL (redistribution layer) on both sides, IPD (integrated passive devices) and SS (stress sensors) is used to support (with microbumps) a stack of four memory chips with TSVs, one thermal chip with heater and one mechanical chip with SS, and then overmolded on its top side for pick and place purposes.

TL;DR: In this article, a set of equivalent thermal conductivity equations for Cu-filled TSVs with various TSV diameters, TSV pitches, and TSV thicknesses, passivation thicknesses and microbump pads were determined.