Showing papers by "Shengdong Zhang published in 2003"

A SPICE model for thin-film transistors fabricated on grain-enhanced polysilicon film

Abstract: A simulation program with integrated circuit emphasis (SPICE)-compatible thin-film transistor (TFT) model for TFTs formed on grain-enhanced polysilicon (poly-Si) film by metal-induced-unilateral crystallization (MIUC) is presented. Due to the regularity of grain structures resulting from the MIUC process, the GBs are organized into a manhattan grid. The specific grain boundary (GB) organization allows a physics-based model to be developed. The model is based on the popular BSIM3 submicron CMOS model framework, which captures most of the physical effects in both long channel and short channel down to the submicron dimension. The model has been verified by a large amount of experimental data and shown to be applicable over a wide range of TFT processes with the application of grain-enhancement techniques such as solid-phase crystallization (SPC) and MIUC.

A self-aligned, electrically separable double-gate MOS transistor technology for dynamic threshold voltage application

Abstract: In this brief, a self-aligned electrically separable double-gate (SA ESDG) MOS transistor technology is proposed and demonstrated. The SA ESDG structure is implemented by defining a dummy top gate that is self-aligned to the bottom gate and then later replacing the dummy using a real top gate. The proposed process is applied to the single-grain Si film formed by recrystallizing a low-pressure chemical vapor deposition a-Si with a metal induced unilateral crystallization technique and enhancing the grain sizes in a subsequent high temperature annealing step. The ideal device structure resulting from the process is verified by scanning electron microscope imaging. The good current-voltage characteristics and the noticeable dynamic threshold voltage effects are also observed in the implemented SA ESDG device.

An elevated source/drain-on-insulator structure to maximize the intrinsic performance of extremely scaled MOSFETs

Abstract: In this paper, a source/drain structure separated from the silicon substrate by oxide isolation is fabricated and studied. The source/drain diffusion regions are connected to the shallow source/drain extension through a smaller opening defined by a double spacer process. Experimental results indicate that the source/drain on insulator significantly reduces the parasitic capacitance. Further optimization by simulation indicates a reduction of series resistance and band-to-band drain leakage at off-state can be achieved in extremely scaled devices. Compared with the conventional planner source/drain structure, the reduction of parasitic capacitance and series resistance can be as much as 80% and 30% respectively.

A viable self-aligned bottom-gate MOS transistor technology for deep submicron 3-D SRAM

Abstract: In this paper, the effect of the nonself-aligned process on the performance variation of a bottom-gate metal oxide semiconductor (MOS) transistor is discussed using a device simulator. The simulation results predict that the nonself-aligned bottom-gate MOS transistor cannot be scaled into the deep submicron regions. A simple fully self-aligned bottom-gate (FSABG) metal oxide semiconductor field effect transistor (MOSFET) technology is then proposed and developed. A new technique for forming thermal oxide on poly-Si serving as the bottom-gate dielectric is also investigated. It is found that the quality of the oxide on the poly-Si recrystallized by the metal induced uni-lateral crystallization (MIUC) is much higher than that by the solid phase crystallization (SPC). Deep submicron fully self-aligned bottom-gate pMOS transistors are fabricated successfully using the proposed technology. The experimentally measured results indicate the device performances depend strongly on the channel-width, and get comparable to that of a single crystal MOSFET if the channel width is less than 0.5/spl mu/m. The effects of the channel width on the device performances are discussed. In addition, the experimental results also confirm that the proposed technology has a good control of the channel film thickness.