S
Shenjie Wang
Researcher at École Polytechnique Fédérale de Lausanne
Publications - 5
Citations - 34
Shenjie Wang is an academic researcher from École Polytechnique Fédérale de Lausanne. The author has contributed to research in topics: Successive approximation ADC & Flash ADC. The author has an hindex of 3, co-authored 5 publications receiving 31 citations. Previous affiliations of Shenjie Wang include Fudan University.
Papers
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Journal ArticleDOI
Design and Implementation of a Rail-to-Rail 460-kS/s 10-bit SAR ADC for the Power-Efficient Capacitance Measurement
Shenjie Wang,Catherine Dehollain +1 more
TL;DR: The specifications of ADC are optimized at system level, emphasizing the ADC following a switched-capacitor capacitance-to-voltage (C2V) converter, to be compatible to the output of C2V, and a bootstrap switch with body effect reduction is adopted to provide the rail- to-rail processing ability.
Journal ArticleDOI
Design and Implementation of a 46-kS/s CMOS SC Dual-Mode Capacitive Sensor Interface With 50-dB SNR and 0.7% Nonlinearity
Shenjie Wang,Catherine Dehollain +1 more
TL;DR: This paper presents the design and implementation of a 46-kS/s CMOS switch-capacitor dual-mode capacitive sensor interface circuit for inkjet-printed capacitive humidity sensors, optimized at system level, emphasizing the C2V operation followed by the data converter.
Proceedings ArticleDOI
Design of a rail-to-rail 460 kS/s 10-bit SAR ADC for capacitive sensor interface
Shenjie Wang,Catherine Dehollain +1 more
TL;DR: A 460 kS/s 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with rail- to-rail input range with energy efficiency of 80 fJ/step is proposed for acquiring capacitive sensor.
Journal ArticleDOI
Design of a parallel low power flash A/D converter for the sub-sampling IR-UWB receiver
TL;DR: This paper presents the design of a dual-channel 4-bit analog-to-digital converter (ADC) for the sub-sampling impulse radio ultra-wideband receiver with the sampling rate of 2.112 GS/s.
Journal ArticleDOI
A termination scheme using intended asymmetric spatial filter response for averaging flash A/D converter
TL;DR: Analysis and simulation show that by tuning the ratio between termination resistor RT and averaging resistor R1, the boundary error is reduced as close as to 1%.