Showing papers in "Analog Integrated Circuits and Signal Processing in 2012"
TL;DR: In this paper, a dynamic latched comparator with offset voltage compensation is presented, which uses one phase clock signal for its operation and can drive a larger capacitive load with complementary version of the regenerative output latch stage.
Abstract: A novel dynamic latched comparator with offset voltage compensation is presented. The proposed comparator uses one phase clock signal for its operation and can drive a larger capacitive load with complementary version of the regenerative output latch stage. As it provides a larger voltage gain up to 22 V/V to the regenerative latch, the input-referred offset voltage of the latch is reduced and metastability is improved. The proposed comparator is designed using 90 nm PTM technology and 1 V power supply voltage. It demonstrates up to 24.6% less offset voltage and 30.0% less sensitivity of delay to decreasing input voltage difference (17 ps/decade) than the conventional double-tail latched comparator at approximately the same area and power consumption. In addition, with a digitally controlled capacitive offset calibration technique, the offset voltage of the proposed comparator is further reduced from 6.03 to 1.10 mV at 1-sigma at the operating clock frequency of 3 GHz, and it consumes 54 μW/GHz after calibration.
68 citations
TL;DR: This is a double-recycling folded cascode (DRFC) operational transconductance amplifier (OTA), demonstrating another phase of significant performance enhancement over the existing fold cascode, recycling folded cascodes and improved recycling folded cascade counterparts.
Abstract: Presented is a double-recycling folded cascode (DRFC) operational transconductance amplifier (OTA), demonstrating another phase of significant performance enhancement over the existing folded cascode, recycling folded cascode and improved recycling folded cascode counterparts. Theoretical treatments and computer simulations under the same 65 nm CMOS technology justify fairly the merits of the proposed DRFC OTA.
61 citations
TL;DR: In this article, an ultra-low-power CMOS symmetrical operational transconductance amplifier (OTA) for low-frequency G m -C applications in weak inversion is presented.
Abstract: In this paper an ultra-low-power CMOS symmetrical operational transconductance amplifier (OTA) for low-frequency G m -C applications in weak inversion is presented. Its common mode input range and its linear input range can be made large using DC shifting and bulk-driven differential pair configuration (without using complex approaches). The symmetrical OTA was successfully verified in a standard CMOS 0.35-μm process. The measurements show an open loop gain of 61 dB and a unit gain frequency of 195 Hz with only 800 mV of power supply voltage and just 40 nW of power consumption. The transconductance is 66 nS, which is suitable for low-frequency G m -C applications.
54 citations
TL;DR: It is demonstrated that even in the presence of the map variations, a TRNG based on the zigzag map passes all of the NIST 800-22 statistical randomness tests using simple post processing of the output data.
Abstract: In this paper, we introduce a novel discrete chaotic map named zigzag map that demonstrates excellent chaotic behaviors and can be utilized in truly random number generators (TRNGs). We comprehensively investigate the map and explore its critical chaotic characteristics and parameters. We further present two circuit implementations for the zigzag map based on the switched current technique as well as the current-mode affine interpolation of the breakpoints. In practice, implementation variations can deteriorate the quality of the output sequence as a result of variation of the chaotic map parameters. In order to quantify the impact of variations on the map performance, we model the variations using a combination of theoretical analysis and Monte-Carlo simulations on the circuits. We demonstrate that even in the presence of the map variations, a TRNG based on the zigzag map passes all of the NIST 800-22 statistical randomness tests using simple post processing of the output data.
45 citations
TL;DR: In this paper, an integrator-based setup was used to extract the four parameters that characterize a single-dispersion Cole-Cole impedance model without direct measurement of the complex impedance.
Abstract: In this letter, we report an integrator-based setup to extract the four parameters that characterize a single-dispersion Cole---Cole impedance model without direct measurement of the complex impedance. Experimental results in the range 100 Hz---1 MHz using apple and plumb fruits are given and results are compared with numerical simulations of the acquired model.
41 citations
TL;DR: In this article, a fully on-chip low-dropout regulator (LDO) comprised of multiple feedback loops to tackle fast load transients is proposed, designed and simulated in 90 nm CMOS technology.
Abstract: Fully integrated voltage regulators with fast transient response and small area overhead are in high demand for on-chip power management in modern SoCs. A fully on-chip low-dropout regulator (LDO) comprised of multiple feedback loops to tackle fast load transients is proposed, designed and simulated in 90 nm CMOS technology. The LDO also adopts an active frequency compensation scheme that only needs a small amount of compensation capacitors to ensure stability. Simulation results show that, by the synergy of those loops, the LDO improves load regulation accuracy to 3 μV/mA with a 1.2 V input and 1 V output. For a 100 mA load current step with the rise/fall time of 100 ps, the LDO achieves maximum output voltage drop and overshoot of less than 95 mV when loaded by a 600 pF decoupling capacitor and consumes an average bias current of 408 μA. The LDO also features a magnitude notch in both its PSRR and output impedance that provides better suppression upon the spectral components of the supply ripple and the load variation around the notch frequency. Monte Carlo simulations are performed to show that the LDO is robust to process and temperature variations as well as device mismatches. The total area of the LDO excluding the decoupling capacitor is about 0.005 mm2. Performance comparisons with existing solutions indicate significant improvements the proposed LDO achieves.
40 citations
TL;DR: In this article, a CFOA-based lossy/lossless floating inductance circuit is introduced, which employs only two CFOAs along with only five passive components.
Abstract: A new CFOA-based lossy/loss-less floating inductance circuit is introduced which, in contrast to previously known configuration requiring three to four CFOAs, employs only two CFOAs along with only five passive components. The workability of the new FI circuit has been demonstrated by using it to design a second order notch filter and a fourth order Butterworth low pass filter by realizing the circuit using commercially available AD844-type CFOAs.
40 citations
TL;DR: This paper presents an efficient structure, based on polyphase filter banks, for CR receivers, a variant of the standard M-path polyphase down converter channelizer that is able to perform M/2-to-1 down sampling of the input time series.
Abstract: A cognitive radio (CR) receiver should be able to filter and simultaneously down convert multiple signals having arbitrary bandwidths and randomly located center frequencies. In this paper we present an efficient structure, based on polyphase filter banks, for CR receivers. Its core, an analysis channelizer, is a variant of the standard M-path polyphase down converter channelizer. It is able to perform M/2-to-1 down sampling of the input time series while it shifts, by aliasing, all the M channels to base-band. A perfect reconstruction (PR) filter is selected as low-pass prototype for avoiding energy losses during the signal processing. A post analysis block is designed for extracting, when necessary, from the base-band aliased channels, the spectra, or their fragments, belonging to different signals. A selector commutes the output ports of the post analysis block that contain spectral fragments of the same bandwidths and properly delivers them to the up converter synthesis channelizers that reassemble them. The synthesis channelizers are Pn-path polyphase up converter modified for performing 1-to-Pn/2 up sampling of the input time series. Complex frequency rotators, placed at the output of the synthesizers, compensate the frequency offsets, applied in the transmitter, that are responsible for the arbitrary center frequency positioning of the received signals. At the end of the receiver chain, arbitrary interpolators resample the base-band centered signals to obtain two samples per symbol needed for the further processing stages.
33 citations
TL;DR: In this article, a catalogue of three generic circuit structures for single current-feedback operational amplifier-based immittance function simulators is presented, where new circuits can be systematically discovered.
Abstract: Using unified representations for single current-feedback operational amplifier based immittance function simulators, new circuits can be systematically discovered. In this article a catalogue of three generic circuit structures is presented. The first structure uses three passive elements to realize either two different grounded lossless negative inductances or two different lossless grounded frequency-dependent positive resistances, and uses four passive elements to realize two different grounded series connected negative resistance and negative inductance. The second structure uses three passive elements to realize a grounded lossless negative inductance and four passive elements to realize either a grounded series connected negative capacitance and a positive resistance or a grounded positive (or negative) series connected inductance and a positive resistance. The third structure uses three passive elements to realize either a grounded negative inductance in series with a negative resistance or a grounded negative capacitance divider in addition to the classical grounded negative impedance converter. Moreover, some of the previously reported immittance function realizations can be systematically obtained from the proposed generic structures.
33 citations
TL;DR: The proposed structure introduces a positive feedback path to achieve a significant boost in transconductance without increasing power or area consumption and results show that the proposed amplifier achieves 400% improvement in gain-bandwidth and 16.6 dB boost in DC gain compared to the conventional folded cascode.
Abstract: This letter is to present a transconductance enhanced recycling structure for folded cascode amplifier. The proposed structure introduces a positive feedback path to achieve a significant boost in transconductance without increasing power or area consumption. A folded cascode amplifier using the proposed structure was implemented in SMIC standard 65 nm CMOS process. Simulation results show that the proposed amplifier achieves 400% improvement in gain-bandwidth and 16.6 dB boost in DC gain compared to the conventional folded cascode.
30 citations
TL;DR: A new technique for CMOS inverter-based tunable transconductors is proposed and offers large transconductance tuning range using a control current and employs the master–slave approach.
Abstract: A new technique for CMOS inverter-based tunable transconductors is proposed in this paper. The proposed technique employs the master---slave approach and offers large transconductance tuning range using a control current. The transconductor was designed using triple-well 0.13 μm CMOS process under the ultra low supply voltage of 0.5 V. The circuit features 37 dB open loop gain, CMRR = 31 dB at each output node, PSRR = 90 dB and GBW = 530 MHz for 120 μA current consumption.
TL;DR: This paper presents techniques to detect, digitize, denoise and classify a certain set of analytes, and demonstrates signal denoising using a discrete wavelet transform based technique.
Abstract: Environmental monitoring relies on compact, portable sensor systems capable of detecting pollutants in real-time. An integrated chemical sensor array system is developed for detection and identification of environmental pollutants in diesel and gasoline exhaust fumes. The system consists of a low noise floor analog front-end (AFE) followed by a signal processing stage. In this paper, we present techniques to detect, digitize, denoise and classify a certain set of analytes. The proposed AFE reads out the output of eight conductometric sensors and eight amperometric electrochemical sensors and achieves 91 dB SNR at 23.4 mW quiescent power consumption for all channels. We demonstrate signal denoising using a discrete wavelet transform based technique. Appropriate features are extracted from sensor data, and pattern classification methods are used to identify the analytes. Several existing pattern classification algorithms are used for analyte detection and the comparative results are presented.
TL;DR: In this paper, the analog CMOS squarer and the four-quadrant analog multiplier are proposed. But the major advantages of the proposed circuits are low voltage supply, multifunction of output, and insensitive to the threshold voltage variation caused by body effect.
Abstract: This paper proposes the analog CMOS squarer and the four-quadrant analog CMOS multiplier. The major advantages of the proposed circuits are low voltage supply, multifunction of output, and insensitive to the threshold voltage variation caused by body effect. The versatile squarer has two inputs (V in and I in ). Its output can be the square of V in or the square of I in . The versatile four-quadrant multiplier has four inputs (V X , I X , V Y , and I Y ). Its output can be the product of V X and V Y , the product of I X and I Y , the product of V X and I Y , or the product of V Y and I X . Therefore, the proposed circuits can be applied more than conventional circuits and have good performance. Second-order effects and frequency response are analyzed. Simulation results have verified the workability of the circuits. Experimental results are done to confirm the operation of the circuits.
TL;DR: In this paper, an automatic gain control (AGC) topology with a variable gain amplifier utilizing a titanium dioxide (TiO2) memristor is described, where a linearized feedback loop amplitude model is used to design the AGC, and a design tradeoff analysis based on distortion performance is developed.
Abstract: An automatic gain control (AGC) topology with a variable gain amplifier utilizing a titanium dioxide (TiO2) memristor is described. A system analysis technique is developed based on the published physical charge-controlled memristor models and unique properties of this passive device. A linearized feedback loop amplitude model is used to design the AGC, and a design tradeoff analysis based on distortion performance is developed. The analysis results are verified with SPICE simulation including a TiO2 memristor SPICE model.
TL;DR: In this article, the authors presented two fully-uncoupled oscillators in which the independent controllability of the frequency of oscillation remains intact even under the influence of the non-ideal parameters/parasitics of the CFOAs employed.
Abstract: There have been two efforts earlier on evolving CFOA-based fully-uncoupled oscillators i.e. circuits in which none of the resistors controlling the frequency of oscillation (FO) appear in the condition of oscillation and vice versa. However, a non-ideal analysis of the earlier known circuits reveals that due to the effect of the parasitic impedances of the CFOAs, the independent controllability of FO is completely destroyed. The main objective of this paper is to present two new fully-uncoupled oscillators in which the independent controllability of the FO remains intact even under the influence of the non-ideal parameters/parasitics of the CFOAs employed. The workability of the proposed circuits has been confirmed by experimental results using AD844-type CFOAs.
TL;DR: In this article, an incremental converter based on a second order ΣΔ modulator is described, which uses a 3-bit DAC with inherent linearity, an optimal reset of integrators and gives rise to an effective offset cancellation with a novel technique based on single or double chopping.
Abstract: This paper describes an incremental converter based on a second order ΣΔ modulator. The scheme uses a 3-bit DAC with inherent linearity, an optimal reset of integrators, and gives rise to an effective offset cancellation with a novel technique based on single or double chopping. The circuit, fabricated in a mixed 0.18-0.6 μm CMOS technology, obtains 1.5-μV residual offset with 2VPP fully differential range. The measured resolution is 19 bit obtained with 512 clock periods.
TL;DR: In this article, the wavelet base is approximated by a systematic algorithm with all the involved approximation parameters taken into account, and the SI filter employing the follow-the-leader feedback (FLF) multiple-loop feedback (MLF) structure is proposed to synthesize the approximation function.
Abstract: A method for realizing wavelet transform (WT) is presented, in which the WT is synthesized by a bank of switched-current (SI) filters whose impulse responses are the basic wavelet function and its dilations. SI circuits are well suitable for this application since the dilation constant across different scales of the transform can be precisely implemented and controlled by the sampling frequency. In this article, the wavelet base is approximated by a systematic algorithm with all the involved approximation parameters taken into account. Also, the SI filter employing the follow-the-leader feedback (FLF) multiple-loop feedback (MLF) structure is proposed to synthesize the approximation function. The Gaussian wavelet is selected as an example to illustrate the design procedure. Simulation results indicate that the proposed method has the merits of high approximation accuracy, strong stability and low sensitivity.
TL;DR: This paper presents the standard-cells synthesis and a comprehensive analysis of various parallel hardware architectures alternatives for SAD calculation, focusing on different design constraints such as high-performance (maximum throughput) and the tradeoff between high- performance and low-power dissipation (namely an isoperformance target).
Abstract: Video applications are increasingly present in consumer electronic devices which require low-power and low-energy consumption. Sum of Absolute Differences (SAD) is the most used distortion metric in video coding implementation and consumes a relative large area in the motion estimation hardware. This paper presents the standard-cells synthesis and a comprehensive analysis of various parallel hardware architectures alternatives for SAD calculation, focusing on different design constraints such as high-performance (maximum throughput) and the tradeoff between high-performance and low-power dissipation (namely an isoperformance target). Low-power techniques supported by commercial standard-cells tools are exercised in this design, such as clock gating, multi-threshold (VT) and a combination of slow and fast standard-cells. We achieved significant power reduction for the architectures with lower frequencies and higher parallelism, slow cells and mainly with only one pipeline stage.
TL;DR: This article presents the algorithms and data structures used to make log-domain decoding of the long LDPC codes specified by the DVB-T2 standard—at the high data rates required for television broadcasting—possible on a modern GPU, and describes a similar decoder implemented on a general purpose CPU.
Abstract: The next generation DVB-T2, DVB-S2, and DVB-C2 standards for digital television broadcasting specify the use of low-density parity-check (LDPC) codes with codeword lengths of up to 64800 bits. The real-time decoding of these codes on general purpose computing hardware is useful for completely software defined receivers, as well as for testing and simulation purposes. Modern graphics processing units (GPUs) are capable of massively parallel computation, and can in some cases, given carefully designed algorithms, outperform general purpose CPUs (central processing units) by an order of magnitude or more. The main problem in decoding LDPC codes on GPU hardware is that LDPC decoding generates irregular memory accesses, which tend to carry heavy performance penalties (in terms of efficiency) on GPUs. Memory accesses can be efficiently parallelized by decoding several codewords in parallel, as well as by using appropriate data structures. In this article we present the algorithms and data structures used to make log-domain decoding of the long LDPC codes specified by the DVB-T2 standard—at the high data rates required for television broadcasting—possible on a modern GPU. Furthermore, we also describe a similar decoder implemented on a general purpose CPU, and show that high performance LDPC decoders are also possible on modern multi-core CPUs.
TL;DR: The inductor analytical characterization is integrated into an optimization-based tool for the automatic design of RF integrated inductors that uses a modified genetic algorithm (MGA) optimization procedure, which has proved its validation in previous work.
Abstract: In this paper an optimization-based approach for the design of RF integrated inductors is addressed. For the characterisation of the inductor behaviour the double ?-model is used. The use of this model is twofold. On one hand it enables the generation of the inductor characterisation in a few seconds. On the other hand its integration into the optimization procedure is straightforward. For the evaluation of the model element values analytical expressions based on technology parameters as well as on the device geometric characteristics are used. The use of a technology-based methodology for the evaluation of the model parameters grants the adaptability of the model to any technology. The inductor analytical characterization is integrated into an optimization-based tool for the automatic design of RF integrated inductors. This tool uses a modified genetic algorithm (MGA) optimization procedure, which has proved its validation in previous work. Due to the design parameter constraints nature as well as the topology constraints, discrete variables optimization techniques are used. The accuracy of the results is checked against a non-commercial software.
TL;DR: Simulation results of the fully differential VCO with positive feedback show that the estimated power consumption, at desired oscillation frequency and under a supply voltage of 3.3 V, is only 7.48 mW.
Abstract: This paper describes a new three-stage voltage controlled ring oscillator (VCO) based on 035 μm standard CMOS technology The VCO was designed for a transmitter operating in the 863–870 MHz European band for wireless sensor applications The transmitter is designed for binary frequency-shift keying (BFSK) modulation, communicating a maximum data rate of 20 kb/s In addition to the VCO, the transmitter combines a BFSK modulator, an up conversion mixer, a power amplifier and an 863–870 MHz band pass filter The modulator uses the frequency hopping spread spectrum and it is intended for short range wireless applications, such as wireless sensor networks The oscillation frequency of the VCO is controlled by a voltage VCTRL Simulation results of the fully differential VCO with positive feedback show that the estimated power consumption, at desired oscillation frequency and under a supply voltage of 33 V, is only 748 mW The proposed VCO exhibits a phase noise lower than −126 dBc/Hz at 10 MHz offset frequency
TL;DR: In this article, a SiAPD-based photoreceiver is proposed for near-infrared spectroscopy (NIRS) applications. But, the design requirements of using CMOS SiAPDs for NIR light detection are discussed, and the challenges of fabricating SiAPd using standard CMOS process are addressed.
Abstract: This paper surveys recent research on CMOS silicon avalanche photodiodes (SiAPD) and presents the design of a SiAPD based photoreceiver dedicated to near-infrared spectroscopy (NIRS) application. Near-infrared spectroscopy provides an inexpensive, non-invasive, and portable means to image brain function, and is one of the most efficient diagnostic techniques of different neurological diseases. In NIRS system, brain tissue is penetrated by near-infrared (NIR) radiation and the reflected signal is captured by a photodiode. Since the reflected NIR signal has very low amplitude, SiAPD is a better choice than regular photodiode for NIR signal detection due to SiAPD`s ability to amplify the photo generated signal by avalanche multiplication. Design requirements of using CMOS SiAPDs for NIR light detection are discussed, and the challenges of fabricating SiAPDs using standard CMOS process are addressed. Performances of state-of-the-art CMOS SiAPDs with different device structures are summarized and compared. The efficacy of the proposed SiAPD based photoreceiver is confirmed by post layout simulation. Finally, the SiAPD and its associated circuits has been implemented in one chip using 0.35 μm standard CMOS technology for an integrated NIRS system.
TL;DR: In this article, the authors describe the design and analysis of an operational transconductance amplifier (voltage to current converter) with wide linear input range, which combines the techniques of signal attenuation and source degeneration in order to reduce the odd order harmonic distortion significantly.
Abstract: The present article describes the design and analysis of an operational transconductance amplifier (voltage to current converter) with wide linear input range. The proposed configuration combines the techniques of signal attenuation and source degeneration in order to reduce the odd order harmonic distortion significantly. The proposed circuit is compared with several circuit topologies based on MOS differential pairs with respect to their achievable linearity, input referred noise and power consumption. The linear transconductor is designed and simulated in 180 nm CMOS process technology with 1.8 V power supply. Simulation results show third order harmonic distortion (HD 3) of ?70 dB for 600 mVpp input signal. For 1% transconductance variation the linear range is about 1.2 Vpp. The input referred noise of the transconductor is $$70\,\hbox{nV}/\sqrt{\text {Hz}}$$ at 10 MHz. The quiescent power consumption is only 450 μW.
TL;DR: In this paper, a flipped voltage follower (FVF) cell with wider bandwidth and lower output impedance is proposed, which is obtained by adding a resistance in the feedback path of conventional FVF.
Abstract: The paper proposes a flipped voltage follower (FVF) cell with wider bandwidth and lower output impedance as compared to the conventional FVF. These improvements are obtained by adding a resistance in the feedback path of conventional FVF. A current mirror is implemented by using proposed FVF cell to verify the performance improvement. The circuits are designed in TSMC 0.18-µm CMOS technology with 1.5 V supply voltage. The simulation results show that bandwidth extension ratio (BWER) of newly developed FVF is 1.4 without peaking and 1.7 with peaking. The BWERs of the passive-compensated current mirror implemented by using proposed FVF cell are 1.28 without peaking and 1.58 with peaking in the frequency response.
TL;DR: In this article, a new true current-mode RMS-to-DC converter circuit based on a square-root-domain squarer/divider and simplified currentmode low pass filter is presented.
Abstract: In this paper a new true current-mode RMS-to-DC converter circuit based on a square-root-domain squarer/divider and simplified current-mode low pass filter is presented. The circuit is designed by employing up-down translinear loop and using of MOSFET transistors that operate in strong inversion saturation region. The converter offer advantages of two-quadrant input current, low circuit complexity, large dynamic range, low supply voltage (1.2 V) and immunity from the body effect. Moreover, the power consumption of the circuit for the maximum accepted input current is less than 100 μW and does not need extra biasing to inject current into transistors. The circuit has been simulated by HSPICE. The simulation results with 0.18 μm CMOS technology are seen to conform to the theoretical analysis and shows benefits of the proposed circuit. Simulation results show high performance of the proposed circuit.
TL;DR: In this article, a fully programmable membership function generator (MFG) is proposed, which is capable of generating triangular, trapezoidal as well as both S-shaped and Z-shaped membership functions simultaneously.
Abstract: In this article, a fully programmable membership function generator (MFG) is proposed. This MFG is capable of generating triangular, trapezoidal as well as both S-shaped and Z-shaped membership functions simultaneously. Utilizing a differential pair as an analog switch leads to relax the design of fuzzy systems control part. This MFG has the ability of adapting itself with various fuzzy controllers which produce different control voltage ranges. Unlike the available reported literatures, this MFG uses a new analog programmable current mirror (APCM) instead of digitally programmable current mirrors to adjust the slopes of membership functions. Extensive time domain simulations have been carried out using Hspice by level 49 parameters (BSIM3v3) in standard CMOS technology to validate the effective performance of the proposed MFG.
TL;DR: In this paper, the authors presented a method of designing active inductors using current-controlled voltage sources (CCVSs). The basic idea consists of designing an equivalent inductor, using only capacitors and CCVSs.
Abstract: This paper presents a novel method of designing active inductors using current-controlled voltage sources (CCVSs). The basic idea consists of designing an equivalent inductor, using only capacitors and CCVSs. The signal-flow graph technique is used for this purpose. The CCVSs are emulated by means of nullator/norator pairs. These elements are then realized using second generation current conveyors (CCIIs), and a combination of CCIIs and operational transconductance amplifiers. In addition, a novel design of simulated inductors using operational transresistance amplifiers is presented. The proposed inductors were used to design filters. SPICE simulations are given to highlight viability and to show good reached results.
TL;DR: This paper describes the theory of operation, mathematical analysis, modeling and circuit design of the true piecewise approximation logarithmic amplifiers and shows better performance than its series linear limit counterpart.
Abstract: This paper describes the theory of operation, mathematical analysis, modeling and circuit design of the true piecewise approximation logarithmic amplifiers. These logarithmic amplifiers can be realized by the series linear limit and parallel summation methods. Both of these methods are discussed in this paper and their transfer functions are extracted. In addition, making use of the proposed formulas, a new mathematical approach is proposed for improving the characteristics of the parallel summation method. All of the presented methods are modeled in Simulink. Moreover, they are designed in a 0.13 μm CMOS technology and simulated by HSPICE. It is observed that analytical results comply with the simulation results. Considering the dynamic range, power, and area, the parallel summation method shows better performance than its series linear limit counterpart.
TL;DR: In this paper, a voltage-mode configuration for low power and simultaneous realization of first-order low-pass, high-pass and all-pass filters is presented, where the output of the all pass filter is taken differentially.
Abstract: In this letter, a new voltage-mode (VM) configuration for providing low-power and simultaneous realization of first-order low-pass, high-pass and all-pass filters is presented. The output of the all-pass filter is taken differentially. The proposed circuit contains low number of components, i.e., only two NMOS transistors, a floating battery, a grounded capacitor and a floating resistor. Adding two NMOS transistors to the proposed circuit it is modified as an all-pass filter with a single-ended output. The main advantage of the presented circuits in comparison with other counterparts is their extremely low power dissipation. Moreover, the floating resistor can be replaced with an additional NMOS transistor in triode region to provide electronic tunability. Simulation results using SPICE program are given to demonstrate the performance of the proposed circuit.
TL;DR: In this article, an inverter based transconductor using double CMOS pair is proposed for implementation of a second order lowpass Gm---C Filter, which is suitable for the wireless specifications of Bluetooth (650 kHz), CDMA 2000 (700 kHz) and Wideband CDMA (2.2 MHz) applications.
Abstract: In this article, an inverter based transconductor using double CMOS pair is proposed for implementation of a second order lowpass Gm---C Filter. The proposed operational transconductance amplifier (OTA) and biquad filter are designed using standard 0.35 μm CMOS technology. Simulation results demonstrate the central frequency tunability from 10 kHz to 2.8 MHz which is suitable for the wireless specifications of Bluetooth (650 kHz), CDMA 2000 (700 kHz) and Wideband CDMA (2.2 MHz) applications. The power consumption of the filter is 445 nW and 178 μW at 10 kHz and 2.8 MHz from 3.3 V supply voltage, respectively. The active area occupied by the designed filter on the silicon is 215 A— 720 μm2. The proposed approach guarantees the upper bound on THD to be Â?40 dB for 300 mVpp signal swing. Employing the double CMOS pair in the inverters causes PSRR to reach 68.6 dB which is higher than similar works.