Showing papers in "The Japan Society of Applied Physics in 2011"

Tunnel Field-Effect Transistor using InAs Nanowire/Si Heterojunction

Abstract: We report on fabrication of tunnel field-effect transistor with III-V nanowire (NW)/Si heterojunction and surrounding-gate structure. The device fabricated by selective-area growth of an n+-InAs/undoped-InAs axial NW on a p+-Si(111) substrate showed switching behavior with an average subthreshold slope (SS) of 104 mV/dec under reverse bias condition. The switching behavior appeared under small supply voltage (Vds=50 mV). Transmission electron microscopy revealed misfit dislocation formed at the interface degraded the SS and ON-state current. Coherent growth without misfit dislocations would promise realization of steep-slope transistor with a SS of <60 mV/dec.

Current Status and Future Challenges of Resistive Switching Memories

Abstract: Resistive switching memories (ReRAM), including transition metal oxide memory (TMO-RAM) and conducting bridge memory (CB-RAM), are some of the most promising new technologies that may scale beyond the charge-storage flash memories. Understanding the fundamental operation mechanism is one important challenge to control the key parameters and to choose the ReRAM material. The knowledge on ReRAM reliability is also insufficient to meet the future challenges. This paper will review the recent major approach of WOX ReRAM and Cu-based CB-RAM. Introduction Conventional charge-storage non-volatile memories are approaching their scaling limit [1]. A number of new non-volatile memories have been proposed [2-5] and among them the resistive switching memory is considered one of the most promising candidates [4-5]. To enable this new technology, researchers and engineers are working on four major topics: write power, scaling possibility, ReRAM materials, and cross point array architecture. The write power of ReRAM is lower than several other emerging memories such as PCM and MRAM [6-8]. However, the high forming voltage/current is still a concern, and even the regular write current affects the bandwidth. Although devices smaller than 10nm have been reported [7-8] recently, but array uniformity and reliability are still not proven. And finally, a proliferation of ReRAM materials has yet to converge to a few exhibiting all desired properties. ReRAM Materials Fig. 1 shows the ReRAM feature size evolution compared with charge-storage memory [7-19]. Already ReRAM has passed the scaling limit of charge-storage memories. Fig. 2 shows the relationship between switching current and speed [7-19]. The observation that only a few points are in the low-current/high-speed region indicates that there may exist a tradeoff between operating current and switching speed. The fact that most of the transition metal oxides can be switched not only in bipolar but also in unipolar modes actually triggers a critical issue on how to choose the best material and the best operation mode. Thus fundamental material studies including the switching mechanism, the conducting mechanism, and the material characteristics are the most important topics in ReRAM research. There seems consensus now that the bipolar switching behavior of TMO-RAM and CB-RAM is dominated by the movement of anions (Valency change effect) and cations (Electrochemical effect) (Fig. 3a and 3b) [9,18]. For unipolar opeation, it is believed that the switching mechanism is based on thermochemical effect (Fig. 3c) [20]. However, the detailed physical models still need further improvements and the knowledge for fine tuning the physical parameters to improve the device performances including speed, current, resistance window, data retention, and cycling endurance is still under development. Field Enhancement Structure for WOX ReRAM Since the forming process is an important issue and needs to be solved, a self-aligned field-enhancement device structure is proposed and its 2D simulation for 20 and 100 nm cells are shown in Fig. 4. By oxidizing the TiN liner into an insulating TiNOX the WOX is forced to protrude above the remaining TiN. Fig. 5a shows significantly higher electric field at the center of the WOX when the size of the W plug scales. Fig. 5b shows that the voltage required for the initial forming process falls rapidly when the cell size scales. Therefore, at 60nm or below, the initial forming process is practically eliminated. The 60nm WOX device not only shows forming-free property, but also good electrical performance. Fig. 6a shows the cycling endurance of the 60nm devices is > 10 times, and a 10X resistance window is well maintained by program-verify algorithms. Excellent thermal stability is Fig.1. Evolution for ReRAM and charge-storage memory. ReRAM shows promising scalability beyond 1X nm technology node. Fig.2. Switching current versus switching time for both TMO-RAM and

Impact of Aspect Ratio on the Subthreshold RTN Amplitude of Multi-Gate MOSFETs

Abstract: In this work, we have investigated the impact of aspect ratio on the RTN amplitude (drain current fluctuation) for multi-gate MOSFETs in the subthreshold regime using TCAD simulations. Our study suggests that, for a given total effective width, the multi-gate device designed with lower aspect ratio (e.g., Tri-gate with AR = 1) may exhibit better immunity to RTN than the higher aspect ratio design (e.g., FinFET with AR = 2.5).

Enabling epitaxy on ultrathin implanted SOI

Abstract: In Fully Depleted Silicon On Insulator (FDSOI) transi stors, the channel thickness is being scaled down with the gat length to insure a good electrostatic control of the gate ove r th channel. Typically for the 20nm node, the transistor integri ty is maintained by keeping the channel thickness below 6nm [1]. Thi s downscaling raises several technological challenges , especially when using an integration scheme in which extensions are implanted before the Raised Source and Drain (RSD) growth (Fig. 1). The challenge lies in finding a viable tradeoff between amorphization and high dopant concentration within t e film. In this paper we present what are the main physical lim itations when implanting the SOI, as well as an efficient way to a lleviate them.

Investigation of the Electrical Properties of Ge/High-k Gate Stack: GeO 2 VS Si-cap

Abstract: Introduction Continuous CMOS area scaling has become a playground for materials scientists as device engineers need to introduce more and more new materials in order to maintain device performance at high level. We have seen in the past years the introduction of high-k/metal gates, and now there is the need for new channel materials, allowing for higher drive current at further scaled VDD [1]. In this last area, Germanium-based MOSFETs have got in the focal point since about several years and interface passivation remains one of the top active challenges in literature. In this work, we will review the electrical properties of two gate stacks, featuring either GeOX– based oxide or Si-cap as passivation layers. Finally, we propose a simple benchmarking plot accounting for the scalability of this alternative gate stacks.

Fast Switching in Magnetic Tunnel Junctions with Double Barrier Layer

Abstract: Memory cells based on electric charge storage, such as flash memory, are rapidly approaching the physical limits of scalability. The spin transfer torque random access memory (STTRAM) is one of the promising candidates for future universal memory [1-6]. The reduction of the current density required for switching and the increase of the switching speed are among the most important challenges in this area. Measurements performed in [4] showed a decrease in the critical current density for the penta-layer magnetic tunnel junction (MTJ) compared with the tri-layer MTJ. To achieve symmetric switching in asymmetric MTJs an external in-plane compensating magnetic field has to be introduced [4]. By numerically investigating the dynamics of the switching process in a MTJ composed of five layers we present the methodology on how to achieve symmetric switching without an external magnetic field by properly engineering the nanopillar geometry. 2. Model Description Our micromagnetic simulations are based on the magnetization dynamics described by the Landau-Lifschitz-Gilbert equation:

Fabrication and Characterization of InP Nanowire Light Emitting Diodes

Abstract: We fabricated nanowire light-emitting diodes (LEDs) using InP nanowires (NWs). Indium phosphide NWs with axial p–n junction were grown by selective-area metalorganic vapor phase epitaxy. The results of secondary-electron-microscopy (SEM) observation and photoluminescence measurement showed the formation of wurtzite InP NWs with some mixture of zincblende crystal phase, as expected from the used growth conditions. NW-LEDs were fabricated by sputtering indium tin oxide (ITO) after a planarization process for the top contact and AuZn evaporation for the backside contact. Current–voltage characterisitics showed clear rectifying characteristics with a small leakage current, and fairly linear current–light output characteristics were observed. By designing the pitch of the NW array, emission from individual NWs was confirmed, which opens the possibility for realizing a single NW-LED applicable to single-photon emitters.

Impacts of Microbump-Induced Local Bending Stress in 3D-LSI

Abstract: 1 Dept. of Bioengineering and Robotics, Graduate School of Engineering, Tohoku Univ. 6-6-01 Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan Phone: +81-22-795-6909 E-mail: link@lbc.mech.tohoku.ac.jp 2 New Industry Creation Hatchery Center (NICHe), Tohoku Univ. 3 Association of Super-Advanced Electronics Technologies (ASET) 4 Dept. of Biomedical Engineering, Graduate School of Biomedical Engineering, Tohoku Univ.

High-Power and High-Gain S-band AlGaN/GaN HFETs with Source Field Plates on Si Substrate

Abstract: 1. Introduction AlGaN/GaN heterojunction field-effect transistors (HFETs) have been widely investigated for high-frequency and high-power applications such as base stations of cellular phones, taking advantages of the superior material properties. Higher gain is also required in such applications, which reduces the number of amplifiers leading to smaller system in size. Introduction of field plate structures in the HFETs increases the gain by reducing gate-drain feedback capacitances (C gd) [1]. However, there has been a limitation of increasing the maximum output power keeping the high gain in the reported devices. In this paper, we present 203W output power with high gain of 16.9dB at 2.5GHz in AlGaN/GaN HFETs on Si substrates with source field plates. The detailed simulation using the device parameters at various biasing conditions reveals that shortening the field plate length achieves high output power together with the high gain, which well agrees with the experimental esults. r

Stack Gate Technique for Feasible Bulk FinFETs

Abstract: Yi-Bo Liao, Meng-Hsueh Chiang, Wei-Chou Hsu, Yu-Sheng Lai, and Hsun Li Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, 701 Tainan, Taiwan Department of Electric Engineering, National Ilan University, 260 I-Lan, Taiwan National Nano Device Laboratories, 300 Hsinchu, Taiwan Phone: +886-9-357400 ext. 653, Fax: +886-9-9369507, E-mail: mhchiang@niu.edu.tw

Si Waveguide-Integrated MSM Ge Photodiode

Abstract: 1 Institute for Photonics-Electronics Convergence System Technology (PECST) 2 Photonics Electronics Technology Research Association (PETRA), West 7 SCR, 16-1, Onogawa, Tsukuba, Ibaraki 305-8569, Japan 3 National Institute of Advanced Industrial Science and Technology (AIST), West 7 SCR, 16-1, Onogawa, Tsukuba, Ibaraki 305-8569, Japan 4 Institute of Industrial Science, The University of Tokyo, 4-6-1, Komaba, Meguro, Tokyo 153-8505, Japan Phone: +81-29-868-6520 E-mail: j-fujikata@petra-jp.org

Effect of Resistance Drift on the Activation Energy for Crystallization in Phase Change Memory

Abstract: The crystallization properties of phase-change memory (PCM) in the presence of thermal disturbances are investigated with a novel micro-thermal stage. It is found that the recrystallization time due to thermal disturbances significantly varies depending on how the PCM cell drifts. The longer crystallization time is obtained following additional resistance drift, which can be described by an increase of the effective activation energy for crystallization. The possibility of achieving better retention in a PCM cell by allowing the PCM cell to drift for a longer time is demonstrated in this work. The activation energy changes at a rate of more than 1 eV/decade with varying time intervals below a second. As the ambient temperature gets higher, the effect of resistance drift on the crystallization process is diminished with respect to the dominant crystallization process which has a higher crystal growth rate at elevated ambient temperatures. # 2012 The Japan Society of Applied Physics