Discover a fresh approach to efficient and insight-driven analog integrated circuit design in nanoscale-CMOS with this hands-on guide. Expert authors present a sizing methodology that employs SPICE-generated lookup tables, enabling close agreement between hand analysis and simulation. This enables the exploration of analog circuit tradeoffs using the gm/ID ratio as a central variable in script-based design flows, and eliminates time-consuming iterations in a circuit simulator. Supported by downloadable MATLAB code, and including over forty detailed worked examples, this book will provide professional analog circuit designers, researchers, and graduate students with the theoretical know-how and practical tools needed to acquire a systematic and re-use oriented design style for analog integrated circuits in modern CMOS.

Systematic Design of Analog CMOS Circuits: Using Pre-Computed Lookup Tables

Systematic design and optimization of operational transconductance amplifier using gm/ID design methodology

Random number generators are an essential part of cryptographic systems. For the highest level of security, true random number generators (TRNG) are needed instead of pseudorandom number generators. In this paper, the stochastic behavior of the spin transfer torque magnetic tunnel junction (STT-MTJ) is utilized to produce a TRNG design. A parallel structure with multiple MTJs is proposed that minimizes device variation effects. The design is validated in a 28-nm CMOS process with Monte Carlo simulation using a compact model of the MTJ. The National Institute of Standards and Technology (NIST) statistical test suite is used to verify the randomness quality when generating encryption keys for the Transport Layer Security or Secure Sockets Layer (TLS/SSL) cryptographic protocol. This design has a generation speed of 177.8 Mbit/s, and an energy of 0.64 pJ is consumed to set up the state in one MTJ.

A true random number generator based on parallel STT-MTJs

Random numbers are widely used in the cryptography and security systems. However, most of the true random number generators (TRNG) which use physical randomness are with high complexity and high power consumption. This paper proposes a new TRNG circuit using magnetic tunnel junction (MTJ). As one of the reliability issues in MTJ based circuit, the stochastic switching behavior provides a perfect physical source of randomness. The functionality of proposed design is validated by transient simulations with 28nm fully depleted silicon-on-insulator (FDSOI) technology and an accurate MTJ compact model. Simulation results show that our design can generate accurate random bitstream stably. The reliability analysis concerning process variation of MTJs and transistors proves the good variability tolerance of our TRNG design. Furthermore, our design can output stable random bitstream around 30 tuning steps.

A novel circuit design of true random number generator using magnetic tunnel junction

This paper presents the design and optimization of a nested-Miller compensated, three-stage operational transconductance amplifier (OTA) for use in switched-capacitor (SC) circuits. Existing design methods for three-stage OTAs often lead to sub-optimal solutions because they decouple inter-related metrics like noise and settling performance. In our approach, the problem of finding an optimal design with the best total integrated noise and settling time has been cohesively solved by formulating a nonlinear constrained optimization program. Equality, inequality, and semi-infinite constraints are formed using closed form symbolic expressions obtained by a closed loop analysis of the SC gain stage and the optimization program is solved by using the interior-point algorithm. For the optimization routine, there is no need to interface with a circuit simulator because all significant device parasitics are included in the model. The optimization and modeling steps are general in nature and can be applied to any amplifier or filter topology. Simulation results show that a 90-nm prototype amplifier achieves a $\pm 0.1{\hbox{\%}}$ dynamic error settling time of 2.5 ns with a total integrated noise of 240 $\mu {\rm V}_{\rm rms}$ , while consuming 5.2 mW from a 1-V power supply.

Settling Time and Noise Optimization of a Three-Stage Operational Transconductance Amplifier

This paper presents a design of a True Random Number Generator (TRNG) using a Spin Transfer Torque Magnetic Tunnel Junction (STT-MTJ) device. Since the probability of the STT-MTJ-based TRNG is locked using a digitally controlled feedback loop, the sensitivity of the feedback gain can be reduced greatly, which eliminates a high-gain amplifier in the feedback loop. It is demonstrated using the circuit simulator (NS-SPICE where the STT-MTJ model is established based on 90nm CMOS/MTJ process technologies) and MATLAB that the random sequences generated from the TRNG become 50%, where the gain of signal converters in the probability-locked loop is the precision of at most 9bit.

Design of an STT-MTJ based true random number generator using digitally controlled probability-locked loop

We propose a design optimization flow for a high-speed and low-power operational transconductance amplifier (OTA) using a gm/ID lookup table design methodology in scaled CMOS. This methodology advantages from using gm/ID as a primary design parameter to consider all operation regions including strong, moderate, and weak inversion regions, and enables the lowest power design. SPICE-based lookup table approach is employed to optimize the operation region specified by the gm/ID with sufficient accuracy for short-channel transistors. The optimized design flow features 1) a proposal of the worst-case design scenario for specification and gm/ID lookup table generations from worst-case SPICE simulations, 2) an optimization procedure accomplished by the combination of analytical and simulation-based approaches in order to eliminate tweaking of circuit parameters, and 3) an additional use of gm/ID subplots to take second-order effects into account. A gain-boosted folded-cascode OTA for a switched capacitor circuit is adopted as a target topology to explore the effectiveness of the proposed design methodology for a circuit with complex topology. Analytical expressions of the gain-boosted folded-cascode OTA in terms of DC gain, frequency response and output noise are presented, and detailed optimization of gm/IDs as well as circuit parameters are illustrated. The optimization flow is verified for the application to a residue amplifier in a 10-bit 125MS/s pipeline A/D converter implemented in a 0.18µm CMOS technology. The optimized circuit satisfies the required specification for all corner simulations without additional tweaking of circuit parameters. We finally explore the possibility of applying this design methodology as a technology migration tool, and illustrate the failure analysis by comparing the differences in the gm/ID characteristics.

Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using g m / I D Lookup Table Methodology

g m /I D Lookup Table Based Operational Transconductance Amplifier Design Featuring Settling Time Optimization

SPICE MOSFET Analog Model Parameter Verification and Re-optimization Based on g m /I D Lookup Table Design Methodology

An active-G m -RC bandpass filter (BPF) with a combined analog-digital tuning system is presented. The active-G m -RC BPF biquad features a positive feedback capacitor to enhance the quality factor, and its required number of OTA per filter-order becomes 0.5. A design example for the application to an on-chip equivalent SAW filter with 60MHz center frequency and 8MHz bandwidth is presented. The proposed tuning system can be enabled with a configurable active-G m -RC BPF/LPF. Behavioral simulations present the proper tuning for the process variation of ±20% in resistors and capacitances, the power can be reduced by a factor of 18.8 over the active-RC BPF.

Takayuki Konishi

Papers

Design of an STT-MTJ based true random number generator using digitally controlled probability-locked loop

Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using g m / I D Lookup Table Methodology

g m /I D Lookup Table Based Operational Transconductance Amplifier Design Featuring Settling Time Optimization

SPICE MOSFET Analog Model Parameter Verification and Re-optimization Based on g m /I D Lookup Table Design Methodology

Active-G m -RC bandpass filter with 60MHz center frequency and a combined analog-digital tuning system