An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Using tabulated thermodynamic data, a comprehensive investigation of the thermo-dynamic stability of binary oxides in contact with silicon at 1000 K was conducted. Reactions between silicon and each binary oxide at 1000 K, including those involving ternary phases, were considered. Sufficient data exist to conclude that all binary oxides except the following are thermodynamically unstable in contact with silicon at 1000 K: Li2O, most of the alkaline earth oxides (BeO, MgO, CaO, and SrO), the column IIIB oxides (Sc2O3, Y2O3, and Re2O3, where Re is a rare earth), ThO2, UO2, ZrO2, HfO2, and Al2O3. Of these remaining oxides, sufficient data exist to conclude that BeO, MgO, and ZrO2 are thermodynamically stable in contact with silicon at 1000 K. Our results are consistent with reported investigations of silicon/binary oxide interfaces and identify candidate materials for future investigations.

https://www.cambridge.org/core/services/aop-cambridge-core/content/view/S0884291400010384

Thermodynamic stability of binary oxides in contact With silicon

Structure and properties of TiN coatings

In fabricating a thin film transistor, an active layer comprising a silicon semiconductor is formed on a substrate having an insulating surface Hydrogen is introduced into The active layer A thin film comprising SiO x N y is formed to cover the active layer and then a gate insulating film comprising a silicon oxide film formed on the thin film comprising SiO x N y  Also, a thin film comprising SiO x N y is formed under the active layer The active layer includes a metal element at a concentration of 1×10 15 to 1×10 19 cm −3 and hydrogen at a concentration of 2×10 19 to 5×10 21 cm −3 

Semiconductor device and method for forming the same

Modern computer microprocessor chips are marvels of engineering complexity. For the current 45 nm technology node, there may be nearly a billion transistors on a chip barely 1 cm2 and more than 10 000 m of wiring connecting and powering these devices distributed over 9-10 wiring levels. This represents quite an advance from the first INTEL 4004B microprocessor chip introduced in 1971 with 10 μm minimum dimensions and 2 300 transistors on the chip! It has been disclosed that advanced microprocessor chips at the 32 nm node will have more than 2 billion transistors.1 For instance, Figure 1 shows a sectional 3D image of a 90 nm IBM microprocessor, containing several hundred million integrated devices and 10 levels of interconnect wiring, designated as the back-end-of-the-line (BEOL). Since the invention of microprocessors, the number of active devices on a chip has been exponentially increasing, approximately doubling every two years. This trend was first described in 1965 by Gordon Moore,2 although the original discussion suggested doubling the number of devices every year, and the phenomenon became popularly known as Moore’s Law. This progress has proven remarkably resilient and has persisted for more than 50 years. The enabler that has permitted these advances is known as scaling, that is, the reduction of minimum device dimensions by lithographic advances (photoresists, tooling, and process integration optimization) by ∼30% for each device generation.3 It allowed more active devices to be incorporated in a given area and improved the operating characteristics of the individual transistors. It should be emphasized that the earlier improvements in chip performance were achieved with very few changes in the materials used in the construction of the chips themselves. The increase of performance with scaling * Corresponding author. E-mail: gdubois@us.ibm.com. † IBM Almaden Research Center. ‡ Stanford University. Willi Volksen received his B.S. in Chemistry (magna cum laude) from New Mexico Institute of Mining and Technology in 1972 and his Ph.D. in Chemistry/Polymer Science from the University of Massachusetts, Lowell, in 1975. He then joined the research group of Prof. Harry Gray/Dr. Alan Rembaum at the California Institute of Technology as a postdoctoral fellow and upon completion of the one-year appointment joined Dr. Rembaum at the Jet Propulsion Laboratory as a Senior Chemist in 1976. In 1977 Dr. Volksen joined the IBM Research Division at the IBM Almaden Research Center in San Jose, CA, where he is an active research staff member in the Advanced Materials Group of the Science and Technology function.

Low dielectric constant materials.

A study of the refractory-gate metallization schemes had been undertaken to provide a low-resistivity metallization for LSI and VLSI. In this paper, we describe an overview of the efforts made in this direction and present two different metallization schemes which lead to a resistivity of ≤20 and 40 µΩ.cm at the gate level. These schemes involve formation of titanium and tantalum silicides on polysilicon gates, respectively. The recommended structure is a metal or a cosputtered alloy/polysilicon/gate oxide/substrate which, when sintered, gives the desired structure silicide/polysilicon/gate oxide substrate. By the use of 1000-A Ti or Ta, the sheet resistance of nearly 1 or 2 Ω/□, respectively, can be routinely obtained. The silicides are mechanically strong and can be dry etched using radial-flow or barrel-type plasma reactors. The Ta silicide structure is found to be very stable throughout standard processing and can be retrofitted in the present processing sequence. Ti silicide structures are similarly stable except for the reactivity of the silicide with HF-containing reagents. The Ti silicide metallization scheme can therefore be employed in processing with changes incorporated to avoid HF-silicide contact.

Refractory silicides of titanium and tantalum for low-resistivity gates and interconnects

A method for making a MOSFET device (20) in a semiconductor body (10) includes the step of forming source and drain contact electrodes (12.1, 12.2) prior to growth of the gate oxide (10.3) and after formation of a high conductivity surface region (10.5). The exposed mutually opposing sidewall edges of each of the contact electrodes (12.1, 12.2) are coated with a sidewall silicon dioxide layer (15.1, 15.2), and the then exposed surface of the semiconductor body (10) between these sidewalls is etched to depth beneath the high conductivity surface region (10.5) in order to separate it into the source and drain regions (10.1, 10.2). Formation of the high conductivity region may be omitted by using Schottky barrier or impurity doped material for the contact electrodes (12.1, 12.2).

Method of fabricating MOS field effect transistors

In order to form MOSFET structures, a cobalt layer (16) is deposited and sintered, at about 400° C. to 500° C., on a patterned semiconductor wafer having exposed polycrystalline (14) or monocrystalline (11) silicon portions, as well as exposed oxide (15 or 25) portions. The cobalt reacts with exposed surfaces of the silicon portions and forms thereat such compounds as cobalt monosilicide (CoSi) or di-cobalt silicide (C02 Si), or a mixture of both. The unreacted cobalt is selectively removed, as by selective etching in a suitable acid bath. A heat treatment at about 700° C. or more, preferably in an oxidizing ambient which contains typically about 2 percent oxygen, converts the cobalt compound(s) into relatively stable cobalt disilicide (CoSi2). Subsequently, deposition of an in situ doped layer (33) of polycrystalline silicon (polysilicon) on the cobalt disilicide contacting the monocrystalline silicon portions--followed by gettering, deposition of a layer (34) of aluminum, and standard etch-patterning of the aluminum and polysilicon layers--completes the metallization of the desired MOSFET structures on the silicon wafer.

Cobalt silicide metallization for semiconductor integrated circuits

A study of the refractory-gate metallization schemes had been undertaken to provide a low-resistivity metallization for LSI and VLSI. In this paper, we describe an overview of the efforts made in this direction and present two different metallization schemes which lead to a resistivity of <=20 and 40 /spl mu//spl Omega/spl dot/cm at the gate level. These schemes involve formation of titanium and tantalum silicides on polysilicon gates, respectively. The recommended structure ia a metal or a cosputtered alloy/polysilicon/gate oxide/substrate which, when sintered, gives the desired structure silicide/polysilicon/gate oxide substrate. By the use of 1000-/spl aring/ Ti or Ta, the sheet resistance of nearly 1 or 2 Omega//spl square/, respectively, can be routinely obtained. The silicides are mechanically strong and can be dry etched using radial-flow or barrel-type plasma reactors. The Ta silicide structure is found to be very stable throughout standard processing and can be retrofitted in the present processing sequence. Ti silicide structures are similarly stable except for the reactivity of the silicide with HF-containing reagents. The Ti silicide metallization scheme can therefore be employed in processing with changes incorporated to avoid HF-silicide contact.

Refractory Silicides of Titanium and Tantalum for Low-Resistivity Gates and Interconnects

Annealing a titanium-rich carbide film deposited on silicon produces, in a single processing step, both a stable titanium silicide contact and a titanium carbide diffusion barrier between the silicide and a subsequently formed overlying layer of aluminum. Reliable low-resistance contacts to VLSI devices are thereby provided in a cost-effective fabrication sequence. Other metallization systems, comprising a silicide and a diffusion barrier to aluminum formed in a single processing step, are also described.

Shyam P. Murarka

Papers

Refractory silicides of titanium and tantalum for low-resistivity gates and interconnects

Method of fabricating MOS field effect transistors

Cobalt silicide metallization for semiconductor integrated circuits

Refractory Silicides of Titanium and Tantalum for Low-Resistivity Gates and Interconnects

Forming low-resistance contact to silicon