The compelling demand for higher performance and lower power consumption in electronic systems is the main driving force of the electronics industry's quest for devices and/or architectures based on new materials. Here, we provide a review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches. We focus on the performance limits and advantages of these materials and associated technologies, when exploited for both digital and analog applications, focusing on the main figures of merit needed to meet industry requirements. We also discuss the use of two-dimensional materials as an enabling factor for flexible electronics and provide our perspectives on future developments.

Electronics based on two-dimensional materials

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III-V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.

Nanometre-scale electronics with III–V compound semiconductors

Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.

/pdf/low-voltage-tunnel-transistors-for-beyond-cmos-logic-3w5c8knrc5.pdf

Low-Voltage Tunnel Transistors for Beyond CMOS Logic

Memory cells are an important building block of digital electronics We combine here the unique electronic properties of semiconducting monolayer MoS2 with the high conductivity of graphene to build a 2D heterostructure capable of information storage MoS2 acts as a channel in an intimate contact with graphene electrodes in a field-effect transistor geometry Our prototypical all-2D transistor is further integrated with a multilayer graphene charge trapping layer into a device that can be operated as a nonvolatile memory cell Because of its band gap and 2D nature, monolayer MoS2 is highly sensitive to the presence of charges in the charge trapping layer, resulting in a factor of 10(4) difference between memory program and erase states The two-dimensional nature of both the contact and the channel can be harnessed for the fabrication of flexible nanoelectronic devices with large-scale integration

Nonvolatile Memory Cells Based on MoS2/Graphene Heterostructures

The main challenges for Tunnel FETs are experimentally demonstrating SS<60 mV/dec, high ON currents and solving their ambipolar behavior. We have experimentally demonstrated a Double-Gate, Strained-Ge, Heterostructure Tunneling FET (TFET) exhibiting very high drive currents and SS<60 mV/dec. Due to small bandgap of s-Ge and the electrostatics of the DG structure, record high drive current of 300 uA/um (the highest ever reported experimentally for a TFET) and a subthreshold slope of ~50 mV/dec was observed. In addition, to address the ambipolar problem and examine the scalability of TFETs, we have developed a sophisticated TFET simulator that uses a Quantum transport model, Non-local BTBT, complete Bandstructure (real and complex) information, and includes all transitions (direct and phonon assisted). Using this simulator, we have studied the scalability of three asymmetric DG TFET configurations (underlapped drain, lower drain doping and lateral heterostructure) in terms of their ability to solve the ambipolar behavior and achieve high ON and low OFF currents.

Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and ≪60mV/dec subthreshold slope

We demonstrated that an ultrathin MgO layer between CoFeB and Ge modulated the Schottky barrier heights and contact resistances of spin diodes. We confirmed that, surprisingly, an insulating MgO layer significantly decreased the Schottky barrier heights and contact resistances of spin diodes on N+Ge, opposite to the increase observed for P+Ge. A 0.5 nm thick MgO layer on N+Ge decreases the Schottky barrier height from 0.47 to 0.05 eV and lowers the minimum contact resistance 100-fold to 1.5×10−6 Ω m2. These results open a pathway for high efficient spin injection from ferromagnetic materials and semiconductors.

The influence of Fermi level pinning/depinning on the Schottky barrier height and contact resistance in Ge/CoFeB and Ge/MgO/CoFeB structures

Cell-to-cell interference constraints dictate that the Floating-gate (FG) of NAND FLASH cells be scaled down to very small thicknesses of a few nm. For the first time, we investigate and quantify the ballistic transport that occurs across ultra-thin poly-Si FGs during programming and experimentally determine its mean free path. This ballistic current has an adverse impact on the reliability of the Inter-poly dielectric (IPD) and potentially limits scaling. We have also demonstrated a solution to this problem in the form of an ultra-thin metal FG and have shown three orders of magnitude lesser ballistic current than poly-Si of same thickness. Further, we have demonstrated functional metal FG down to 3 nm.

Investigation of ballistic current in scaled Floating-gate NAND FLASH and a solution

Systems and methods of managing defects in nonvolatile storage systems that can be used to avoid an inadvertent loss of data, while maintaining as much useful memory in the nonvolatile storage systems as possible. The disclosed systems and methods can monitor a plurality of trigger events for detecting possible defects in one or more nonvolatile memory (NVM) devices included in the nonvolatile storage systems, and apply one or more defect management policies to the respective NVM devices based on the types of trigger events that resulted in detection of the possible defects. Such defect management policies can be used proactively to retire memory in the nonvolatile storage systems with increased granularity, focusing the retirement of memory on regions of nonvolatile memory that are likely to contain a defect.

Defect management policies for nand flash memory

Strain and confinement leads to reduction in m* to numbers comparable with electron mass in III–V's. Room temperature mobility of 960/860cm2/Vs for In 0.41 Ga 0.59 Sb/GaSb channels (NS=1x1012/cm2) are the highest reported for these materials. μh is ≫ 3X compared to uniaxially strained Si. Further enhancement should be possible using uniaxial strain (Fig. 3). High μh Sb-based channels along with their already reported excellent n-channel performance [1] make them promising candidates to meet ITRS requirements for future nodes.

Shyam Sunder Raghunathan

Papers

Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and ≪60mV/dec subthreshold slope

The influence of Fermi level pinning/depinning on the Schottky barrier height and contact resistance in Ge/CoFeB and Ge/MgO/CoFeB structures

Investigation of ballistic current in scaled Floating-gate NAND FLASH and a solution

Defect management policies for nand flash memory

Engineering of strained III–V heterostructures for high hole mobility