An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III-V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.

Nanometre-scale electronics with III–V compound semiconductors

The formation of the Schottky barrier height (SBH) is a complex problem because of the dependence of the SBH on the atomic structure of the metal-semiconductor (MS) interface. Existing models of the SBH are too simple to realistically treat the chemistry exhibited at MS interfaces. This article points out, through examination of available experimental and theoretical results, that a comprehensive, quantum-mechanics-based picture of SBH formation can already be constructed, although no simple equations can emerge, which are applicable for all MS interfaces. Important concepts and principles in physics and chemistry that govern the formation of the SBH are described in detail, from which the experimental and theoretical results for individual MS interfaces can be understood. Strategies used and results obtained from recent investigations to systematically modify the SBH are also examined from the perspective of the physical and chemical principles of the MS interface.

The physics and chemistry of the Schottky barrier height

Printable electronics present a new era of wearable electronic technologies. Detailed technologies consisting of novel ink semiconductor materials, flexible substrates, and unique processing methods can be integrated to create flexible sensors. To detect various stimuli of the human body, as well as specific environments, unique electronic devices formed by "ink-based semiconductors" onto flexible and/or stretchable substrates have become a major research trend in recent years. Materials such as inorganic, organic, and hybrid semiconductors with various structures (i.e., 1D, 2D and 3D) with printing capabilities have been considered for bio and medical applications. In this review, we report recent progress in materials and devices for future wearable sensor technologies.

Recent Progress in Materials and Devices toward Printable and Flexible Sensors

A key element in the integration of microprocessor chips with optical communications circuits is a photodetector to mediate the optical and electronic signals. Germanium photodetectors are very attractive in this regard because they are compatible with conventional silicon circuitry, but they suffer from noise that limits their performance. Assefa et al. now show how the poor intrinsic noise characteristics of germanium can be overcome through the careful engineering of optical and electrical fields at the nanometre scale. The result is a compact and efficient photodetector that could enable a range of optoelectronic applications. To integrate microchips with optical communications a photodetector is required to mediate the optical and electronic signals. Although germanium photodetectors are compatible with silicon their performance is impaired by poor intrinsic noise. Here the noise is reduced by nanometre engineering of optical and electrical fields to produce a compact and efficient photodetector. Integration of optical communication circuits directly into high-performance microprocessor chips can enable extremely powerful computer systems1. A germanium photodetector that can be monolithically integrated with silicon transistor technology2,3,4,5,6,7,8 is viewed as a key element in connecting chip components with infrared optical signals. Such a device should have the capability to detect very-low-power optical signals at very high speed. Although germanium avalanche photodetectors9,10 (APD) using charge amplification close to avalanche breakdown can achieve high gain and thus detect low-power optical signals, they are universally considered to suffer from an intolerably high amplification noise characteristic of germanium11. High gain with low excess noise has been demonstrated using a germanium layer only for detection of light signals, with amplification taking place in a separate silicon layer12. However, the relatively thick semiconductor layers that are required in such structures limit APD speeds to about 10 GHz, and require excessively high bias voltages of around 25 V (ref. 12). Here we show how nanophotonic and nanoelectronic engineering aimed at shaping optical and electrical fields on the nanometre scale within a germanium amplification layer can overcome the otherwise intrinsically poor noise characteristics, achieving a dramatic reduction of amplification noise by over 70 per cent. By generating strongly non-uniform electric fields, the region of impact ionization in germanium is reduced to just 30 nm, allowing the device to benefit from the noise reduction effects13,14,15 that arise at these small distances. Furthermore, the smallness of the APDs means that a bias voltage of only 1.5 V is required to achieve an avalanche gain of over 10 dB with operational speeds exceeding 30 GHz. Monolithic integration of such a device into computer chips might enable applications beyond computer optical interconnects1—in telecommunications16, secure quantum key distribution17, and subthreshold ultralow-power transistors18.

Reinventing germanium avalanche photodetector for nanophotonic on-chip optical interconnects

Schottky barrier height modulation in metal/Ge Schottky junction was demonstrated by inserting an ultrathin interfacial silicon nitride layer. The SiN interfacial layer suppressed strong Fermi level pinning in metal/Ge Schottky junction, which resulted in effective control of Schottky barrier height. Metal/SiN/Ge Schottky diode was systematically investigated in terms of SiN thickness dependence and metal work function dependence. At an optimal SiN thickness, Ohmic contact between metal and Ge was obtained as a result of Fermi level depinning, and almost ideal Schottky barrier height determined by the work function difference between the metal and Ge was achieved. This technology was finally applied to metal source/drain Ge metal-oxide-semiconductor field-effect-transistors with low source/drain resistance.

Fermi level depinning in metal/Ge Schottky junction for metal source/drain Ge metal-oxide-semiconductor field-effect-transistor application

GeO2 was grown by a slot-plane-antenna (SPA) high density radical oxidation, and the oxidation kinetics of radical oxidation GeO2 was examined. By the SPA radical oxidation, no substrate orientation dependence of growth rate attributed to highly reactive oxygen radicals with low oxidation activation energy was demonstrated, which is highly beneficial to three-dimensional structure devices, such as multigate field-effect transistors, to form conformal gate dielectrics. The electrical properties of an aluminum oxide (Al2O3) metal-oxide-semiconductor gate stack with a GeO2 interfacial layer were investigated, showing very low interface state density (Dit), 1.4×1011 cm−2 eV−1. By synchrotron radiation photoemission spectroscopy, the conduction and the valence band offsets of GeO2 with respect to Ge were estimated to be 1.2±0.3 and 3.6±0.1 eV, which are sufficiently high to suppress gate leakage.

Radical oxidation of germanium for interface gate dielectric GeO2 formation in metal-insulator-semiconductor gate stack

Organic or carbon semiconductor devices are promising for both nanoelectronic and macroelectronic applications. One of the major challenges to achieve high performance of these devices lies on understanding and improving the metal-organic (M/O) interface. In this paper, we present evidence and demonstration of Fermi-level depinning at the M/O interface by inserting an ultrathin interfacial ${\text{Si}}_{3}{\text{N}}_{4}$ insulator in between. The M/O contact behavior is successfully tuned from rectifying to quasi-Ohmic and to tunneling by varying the ${\text{Si}}_{3}{\text{N}}_{4}$ thickness within 0\char21{}6 nm. Detailed physical mechanisms of Fermi-level pinning/depinning responsible for the M/O contact behavior are clarified based on a lumped-dipole model and a simple depinning model. This work sheds light on the fundamental understanding of the M/O interface properties and also proves a practical engineering method of achieving low-resistance quasi-Ohmic contacts for organic electronic devices.

Contact engineering for organic semiconductor devices via Fermi level depinning at the metal-organic interface

Rapid melt growth was used to fabricate gate-all-around germanium-on-insulator (GeOI) p-MOSFETs with plasma-nitrided Ge surface, Al2O3 high-k gate dielectric, and self-aligned NiGe contacts. The subthreshold swing is 71 mV/dec, which is better than those of the bulk and nanowire Ge p-MOSFETs reported to date. Planar GeOI p-MOSFET arrays show 40% hole mobility enhancement at a high effective field, which is as good as bulk Ge devices.

High-Performance Gate-All-Around GeOI p-MOSFETs Fabricated by Rapid Melt Growth Using Plasma Nitridation and ALD $\hbox{Al}_{2}\hbox{O}_{3}$ Gate Dielectric and Self-Aligned NiGe Contacts

We successfully demonstrate Ge pMOSFET integrated on Si. In this process, Ge is grown selectively on Si on patterned SiO2 by heteroepitaxy, and pMOSFET is fabricated with gate dielectric stack consisting of thin GeO2 and Al2O3 and Al metal gate electrode. Fabricated devices show ~80% enhancement over the Si universal hole mobility. These results are promising toward monolithically integrating Ge MOSFETs with Si CMOS VLSI platform.

Masaharu Kobayashi

Papers

Fermi level depinning in metal/Ge Schottky junction for metal source/drain Ge metal-oxide-semiconductor field-effect-transistor application

Radical oxidation of germanium for interface gate dielectric GeO2 formation in metal-insulator-semiconductor gate stack

Contact engineering for organic semiconductor devices via Fermi level depinning at the metal-organic interface

High-Performance Gate-All-Around GeOI p-MOSFETs Fabricated by Rapid Melt Growth Using Plasma Nitridation and ALD $\hbox{Al}_{2}\hbox{O}_{3}$ Gate Dielectric and Self-Aligned NiGe Contacts

p-Channel Ge MOSFET by Selectively Heteroepitaxially Grown Ge on Si