Showing papers by "Souvik Mahapatra published in 2000"

Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs

Abstract: The influence of channel length and oxide thickness on the hot-carrier induced interface (N/sub it/) and oxide (N/sub ot/) trap profiles is studied in n-channel LDD MOSFET's using a novel charge pumping (CP) technique. The technique directly provides separate N/sub it/ and N/sub ot/ profiles without using simulation, iteration or neutralization, and has better immunity from measurement noise by avoiding numerical differentiation of data. The N/sub it/ and N/sub ot/ profiles obtained under a variety of stress conditions show well-defined trends with the variation in device dimensions. The N/sub it/ generation has been found to be the dominant damage mode for devices having thinner oxides and shorter channel lengths. Both the peak and spread of the N/sub it/ profiles have been found to affect the transconductance degradation, observed over different channel lengths and oxide thicknesses. Results are presented which provide useful insight into the effect of device scaling on the hot-carrier degradation process.

A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique

Abstract: A novel simulation-independent charge pumping (CP) technique is employed to accurately determine the spatial distributions of interface (N/sub it/) and oxide (N/sub 0t/) traps in hot-carrier stressed MOSFETs. Direct separation of N/sub it/ and N/sub 0t/ is achieved without using simulation, iteration, or neutralization. Better immunity from measurement noise is achieved by avoiding numerical differentiation of data. The technique is employed to study the temporal buildup of damage profiles for a variety of stress conditions. The nature of the generated damage and trends in its position are qualitatively estimated from the internal electric field distributions obtained from device simulations. The damage distributions are related to the drain current degradation and well-defined trends are observed with the variations in stress biases and stress time. Results are presented which provide fresh insight into the hot-carrier degradation mechanisms.

Role of inversion layer quantization on sub-bandgap impact ionization in deep-sub-micron n-channel MOSFETs

Abstract: Impact ionization in n-channel MOSFETs for drain voltages (V/sub D/) below the bandgap voltages (qV/sub D/

Drain Bias Dependence of Gate Oxide Reliability in Conventional and Asymmetrical Channel MOSFETs in the Low Voltage Regime

Abstract: Drain bias dependence of gate oxide reliability is investigated on conventional (CON) and Lateral Asymmetric Channel (LAC) MOSFETs for low drain voltages that correspond to the real operating voltages for deep-sub-micron devices. For short channel devices, the oxide reliability improves drastically as drain bias increases. Device simulations showed that the vertical field distribution in the oxide is asymmetric for non-zero drain biases and this results in an asymmetric gate current distribution with the peak at the source end. By introducing an intentionally graded doping profile along the channel (LAC), the asymmetry in the vertical filed distribution can be enhanced with consequent improvement in gate oxide reliability.

Reliability studies on sub 100 nm SOI-MNSFETs

Abstract: SOI MNSFETs with channel lengths down to 100 nm and having a Jet Vapor Deposited (JVD) silicon nitride (Si/sub 3/N/sub 4/) gate dielectric are fabricated and characterized. The JVD MNSFETs show comparable performance in comparison to conventional SiO/sub 2/ SOI-MOSFETs, in terms of low gate leakage, Si/sub 3/N/sub 4//Si interface quality and I/sub on//I/sub off/ ratio. In addition, the MNSFETs show better hot carrier reliability compared to conventional MOSFETs. Our results explore the worthiness of JVD Si/sub 3/N/sub 4/ as gate dielectric for future low power ULSI applications.