This paper describes the ATLAS experiment as installed in i ts experimental cavern at point 1 at CERN. It also presents a brief overview of the expec ted performance of the detector.

http://absimage.aps.org/image/SES08/MWS_SES08-2008-020010.pdf

The ATLAS Experiment at the CERN Large Hadron Collider

This ebook is the first authorized digital version of Kernighan and Ritchie's 1988 classic, The C Programming Language (2nd Ed.). One of the best-selling programming books published in the last fifty years, "K&R" has been called everything from the "bible" to "a landmark in computer science" and it has influenced generations of programmers. Available now for all leading ebook platforms, this concise and beautifully written text is a "must-have" reference for every serious programmers digital library.

As modestly described by the authors in the Preface to the First Edition, this "is not an introductory programming manual; it assumes some familiarity with basic programming concepts like variables, assignment statements, loops, and functions. Nonetheless, a novice programmer should be able to read along and pick up the language, although access to a more knowledgeable colleague will help."

The C programming language

A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for flicker (1/f) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit. This is validated by simulation and measurement. Straightforward expressions for period jitter and phase noise enable manual design of a ring oscillator to specifications, and guide the choice between ring and LC oscillator

http://venividiwiki.ee.virginia.edu/mediawiki/images/c/c2/A_abidi.pdf

Phase Noise and Jitter in CMOS Ring Oscillators

Design strategy and efficiency optimization of ultrahigh-frequency (UHF) micro-power rectifiers using diode-connected MOS transistors with very low threshold voltage is presented. The analysis takes into account the conduction angle, leakage current, and body effect in deriving the output voltage. Appropriate approximations allow analytical expressions for the output voltage, power consumption, and efficiency to be derived. A design procedure to maximize efficiency is presented. A superposition method is proposed to optimize the performance of multiple-output rectifiers. Constant-power scaling and area-efficient design are discussed. Using a 0.18-mum CMOS process with zero-threshold transistors, 900-MHz rectifiers with different conversion ratios were designed, and extensive HSPICE simulations show good agreement with the analysis. A 24-stage triple-output rectifier was designed and fabricated, and measurement results verified the validity of the analysis

Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications

With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance. 

Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to enhance dramatically chip performance and functionality, while reducing the distance among devices on a chip. They promise solutions to the current "interconnect bottleneck" challenges faced by IC designers. They also may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. 

This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of three-dimensional integrated circuits.




* Demonstrates how to overcome "Interconnect Bottleneck" with 3D Integrated Circuit Design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers.
* The FIRST book on 3D Integrated Circuit Design...provides up-to-date information that is otherwise difficult to find;
* Focuses on design issues key to the product development cyle...good design plays a major role in exploiting the implementation flexibilities offered in the third dimension;
* Provides broad coverage of 3D IC Design, including Interconnect Prediction Models, Thermal Management Techniques, and Timing Optimization...offers practical view of designing 3D circuits.

Three-Dimensional Integrated Circuit Design

In this paper an accurate, analytical model for the evaluation of the CMOS inverter transient response and propagation delay for short-channel devices is presented. An exhaustive analysis of the inverter operation is provided which results in accurate expressions of the output response to an input ramp. Most of the factors which influence the inverter operation are taken into account. The /spl alpha/-power law MOS model, which considers the carriers' velocity saturation effects of short-channel devices, is used. The final results are in excellent agreement with SPICE simulations.

Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices

This paper introduces a new, accurate analytical model for the evaluation of the delay and the short-circuit power dissipation of the CMOS inverter. Following a detailed analysis of the inverter operation, accurate expressions for the output response to an input ramp are derived. Based on this analysis improved analytical formulae for the calculation of the propagation delay and short-circuit power dissipation, are produced. Analytical expressions for all inverter operation regions and input waveform slopes are derived, which take into account the influences of the short-circuit current during switching, and the gate-to-drain coupling capacitance. The effective output transition time of the inverter is determined in order to map the real output voltage waveform to a ramp waveform for the model to be applicable in an inverter chain. The final results are in very good agreement with SPICE simulations.

Propagation delay and short-circuit power dissipation modeling of the CMOS inverter

Edge detection is one of the most fundamental algorithms in digital image processing. The Canny edge detector is the most implemented edge detection algorithm because of its ability to detect edges even in images that are intensely contaminated by noise. However, this is a time consuming algorithm and therefore its implementations are difficult to reach real time response speeds. Especially nowadays where the demand for high resolution image processing is constantly increasing, the need for fast and efficient edge detector implementations is ever so present. A new parallel Canny edge detector FPGA implementation is proposed in this paper to answer this demand. This design takes advantage of 4-pixel parallel computations to achieve high throughput without increasing the on-chip memory demands. Synthesis and simulation results are presented to prove the design's efficiency and high frames per second rate.

Real-time canny edge detection parallel implementation for FPGAs

A power consumption measurement framework for embedded processing systems is presented in this work. Given an assembly or machine level program as input to this setup, the energy consumption of the specific program in the specific processing systems may be estimated. The instruction level power models are derived based on the power supply current measurement technique. The instantaneous variations of the power supply current provide the appropriate information for the accurate estimation of the power consumption at different operating situations of the processor (core) and of the overall processing system as well (consumption of peripheral units). The proposed instantaneous current measuring approach, along with the execution of special test programs for analysis of inter-instruction effects provides a clear insight into the power behavior of embedded processing systems.

Instruction-level power consumption estimation embedded processors low-power applications

The problem of estimating the performance of CMOS gates driving RC interconnect loads is addressed in this paper. The widely accepted /spl pi/-model is used for the representation of an interconnect line that is driven by an inverter. The output waveform and the propagation delay of the inverter are analytically calculated taking into account the coupling capacitance between input and output and the effect of the short-circuit current. In addition, short-circuit power dissipation is accurately estimated. Once the voltage waveform at both the beginning and the end of an interconnect line are obtained, a simple method is employed in order to calculate the voltage waveform at each point of the line.

Spiridon Nikolaidis

Papers

Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices

Propagation delay and short-circuit power dissipation modeling of the CMOS inverter

Real-time canny edge detection parallel implementation for FPGAs

Instruction-level power consumption estimation embedded processors low-power applications

Modeling CMOS gates driving RC interconnect loads