Showing papers by "Srinivas Devadas published in 1992"

Estimation of average switching activity in combinational and sequential circuits

Abstract: The authors address the problem of estimating the average power dissipated in VLSI combinational and sequential circuits, under random input sequences. Switching activity is strongly affected by gate delays and for this reason a general delay model is used in estimating switching activity. The method takes into account correlation caused at internal gates in the circuit due to reconvergence of input signals. In sequential circuits, the input sequence applied to the combinational portion of the circuit is highly correlated because some of the inputs to the combinational logic are flip-flop outputs representing the state of the circuit. Methods are presented to probabilistically estimate switching activity in sequential circuits. These methods automatically compute the switching rates and correlations between flip-flop outputs. >

Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation

Abstract: It is shown that a simplified model of power dissipation relates maximizing dissipation to maximizing gate output activity, appropriately weighted to account for differing load capacitances. To find the input or input sequence that minimizes the weighted activity, algorithms are given for transforming the problem to a weighted max-satisfiability problem, and exact and approximate algorithms for solving weighted max-satisfiability are presented. Algorithms for constructing the max-satisfiability problem for both dynamic and static CMOS, where for the latter dissipation caused by glitching is considered, are presented. The authors present efficient exact and approximate methods for solving weighted max-satisfiability and show that these methods are viable for large-scale problems through examination of experimental results. >

On average power dissipation and random pattern testability of CMOS combinational logic networks

Abstract: We explore the implications of the observation that the probability of the occurrence of a transition on a wire of a circuit affects both the average power dissipation and the random pattern testability of a circuit. We show that restructuring a logic circuit can significantly affect its average power dissipation. We present various methods for the synthesis of combinational logic networks, and show the effect of different algorithms on the power dissipation of the circuit. We also focus on the dual problem of improving the random pattern testability of logic circuits. We show that modifying the signal probabilities can significantly affect the random pattern testability of a circuit.

Synthesis of robust delay-fault-testable circuits: theory

Abstract: The authors give a comprehensive theoretical framework for the analysis and synthesis of delay-fault-testable combinational logic circuits. For each of the common models of delay-fault testability, robust gate-delay faults and robust path-delay faults, they provide the necessary and sufficient conditions for complete testability under that model for two-level circuits. The authors describe the conditions in terminology common to two-level minimization and show their relationship to properties produced by two-level minimizers. Similar conditions for multilevel networks are presented. It is shown that constrained algebraic factorization is required to retain complete gate-delay-fault testability beginning from a two-level network. The authors present preliminary experimental results using these synthesis techniques. >

Certified timing verification and the transition delay of a logic circuit

Abstract: The transition delay of a circuit is examined. It is shown that the transition delay of a circuit can differ from the floating delay even in the presence of arbitrary monotonic speedups in the circuit. This result is used to derive a procedure which directly computes the transition delay of a circuit. Experimental results of applying the transition delay computation procedure to a number of benchmark examples are given. The most practical benefit of this procedure is that it not only results in a delay calculation but also produces a vector sequence that may be timing simulated to certify static timing verification. >

Synthesis of robust delay-fault-testable circuits: practice

Abstract: The authors show how an orchestration of combinational synthesis for testability approaches can result in logic-level implementations of large integrated circuit designs that are completely robustly gate-delay-fault and path-delay-fault testable. For control portions of VLSI circuits, Boolean covering and algebraic factorization procedures that guarantee path-delay-fault testability are used, starting from a sum-of-products representation of a function. Hierarchical composition rules are used in the synthesis of regular structures occurring in data path portions, such as parity generators and arithmetic units. It is shown how test vectors to detect all path delay faults can be obtained as a by-product of the synthesis process. These techniques were used on circuits with over 5000 gates, and preliminary experimental results on a data encryption chip, a small microprocessor, and a speech recognition chip are presented. >

Statistical timing analysis of combinational circuits

Abstract: The authors develop efficient methods for computing an exact probability distribution of the delay of a combinational circuit, given probability distributions for the gate and wire delays. The derived distribution can give the probability that a combinational circuit will achieve a certain performance, across the possible range. The techniques target fast analysis as well as reduced memory requirements. The authors define a notion of falsity of paths when dealing with probability distributions on gate and wire delays, and they give methods for identifying and ignoring false paths in their probabilistic analysis, so as to obtain correct and accurate answers to the performance prediction question. Some results and comparisons are given for a number of combinational circuit benchmarks. >

Validatable nonrobust delay-fault testable circuits via logic synthesis

Abstract: The authors advocate a synthesis approach to delay-fault testing, wherein completely path-delay-fault testable circuits are automatically synthesized, meeting area and performance requirements. They give necessary and sufficient conditions for validatable nonrobust fault testability of paths in arbitrary multilevel networks. Validatable nonrobust testing as opposed to robust testing offers degrees of freedom that enable the development of efficient synthesis procedures that target delay-fault testability, and also provides a means of producing compact test vector sets. The authors then focus on the development of synthesis procedures that produce networks that are fully testable under the nonrobust fault model. They show that primality and irredundancy are both a necessary and sufficient condition for complete validatable nonrobust testability in the two-level case. They prove that synthesizing a multilevel network using algebraic factorization retains complete validatable nonrobust testability. Preliminary results that verify the procedures are reported. >

Basic Definitions and Concepts

Abstract: Most of the terminology used in this book is standard and in common use in the synthesis community [54, 13, 14]. This chapter is devoted to the definition of the nontrivial terminology and an elucidation of some of the basic concepts.

Verification of asynchronous interface circuits with bounded wire delays

Abstract: We address the problem of verifying that the gate-level implementation of an asynchronous circuit, with given or extracted bounds on wire and gate delays, is equivalent to a specification of the asynchronous circuit behavior described as a classical flow table. We give a procedure to extract the complete set of possible flow tables from a gate-level description of an asynchronous circuit under the bounded wire delay model. Given an extracted flow table and the initial flow table specification, we give procedures to construct a product flow table so as to check for machine equivalence under various modes of operation.

Automatic generation and verification of sufficient correctness properties for synchronous processors

Abstract: A general strategy for automatically generating and verifying sufficient correctness properties for a broad class of synchronous processors is presented. Given a particular specification and implementation pair, it is shown how basic correctness properties can be algorithmically translated into a set of computation tree logic (CTL) formulae which are sufficient for equivalence between the behavioral and logic descriptions. Preliminary experimental results on the verification of microcoded and array processors are presented. >

Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks

Abstract: The authors address the problem of synthesizing circuits that are highly testable for transistor stuck-open fault testability in arbitrary, multilevel networks. They consider single stuck-open faults that are detectable using two-pattern tests, under a robust fault model wherein hazards, races, or glitches cannot invalidate a test. Using these results the authors show that algebraic factorization, including the constrained use of the complement, can be used to synthesize fully-stuck-open-fault testable multilevel networks. They provide a comprehensive set of practical results. >

Finite State Machine Decomposition

Abstract: Finite state machine (FSM) decomposition is concerned with the implementation of a FSM as a set of smaller interacting submachines. Such an implementation is desirable for a number of reasons. A partitioned sequential circuit usually leads to improved performance as a result of a reduction in the longest path between latch inputs and outputs. This fact is particularly true when the individual submachines are implemented as Programmable Logic Arrays (PLAs). It appears that the primary interest in using decomposition tools in industry stems from a need to improve the performance of FSM controllers, which often dictates the required duration of the system clock. FSM decomposition can be applied directly when Programmable Gate Array (PGAs) or Programmable Logic Devices (PLDs) are the target technology. Such technologies are characterized by I/O or gate-limited blocks of logic and latches into which the circuit must be mapped. In many cases, it is desirable for reasons of clock-skew minimization or simplifying the layout to distribute the control logic for a data path in such a manner that the portions of the data path and control that interact closely are placed next to each other. FSM decomposition can also be used for this purpose. Partitioning of the logic implementing the FSM could result in simplified layout constraints resulting in smaller chip area. In PLA-based FSMs, decomposition has the effect of partitioning the PLA that implements the original FSM into smaller interacting PLAs that implement the individual submachines. In such situations, an area reduction can be attributed to PLA partitioning. Finally, it is not computationally feasible for current multilevel logic minimizers (e.g. MIS-II [10]) to search all possible area minimal solutions. In some cases, an initially-decomposed FSM could correspond to a superior starting point for multilevel logic minimization.

Sequential Test Generation

Abstract: Test generation for sequential circuits has long been recognized as a difficult problem [16, 68, 91]. In particular, unstructured, random, sequential digital designs are very difficult to test. The test generation problem is difficult mainly because the input space that must be searched to obtain a test vector sequence is huge. Since most circuits have a large number of inputs, it is not possible to enumerate the input space explicitly. The structure of the circuit must be exploited to search the input space implicitly and reduce the complexity of the search process for the expected cases. Another difficulty in circuits without reset lines is the necessity of initializing the latches to a known value.

Heuristic minimization of Boolean relations using testing techniques

Abstract: A Boolean relation is a one-to-many multioutput Boolean mapping and is a generalization of incompletely specified logic functions. Boolean relations arise in several contexts (for instance, in a finite state machine with sets of equivalent states). Minimization of Boolean relations is important from the point of view of synthesis, especially synthesis for testability. A fast heuristic procedure for finding an optimal sum-of-products representation for a function compatible with a Boolean relation is described. Starting with an initial function compatible with the relation, a process of iterative logic improvement based on test generation techniques is used to derive a minimal function. >