S
Srinivasa Konala
Researcher at University of Kentucky
Publications - 6
Citations - 399
Srinivasa Konala is an academic researcher from University of Kentucky. The author has contributed to research in topics: Programmable logic device & Field-programmable gate array. The author has an hindex of 6, co-authored 6 publications receiving 397 citations.
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Proceedings ArticleDOI
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)
TL;DR: A new approach for Field Programmable Gate Array (FPGA) testing is presented that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test, achieving BIST without any area overhead or performance penalties to the system function implemented by the FPGA.
Proceedings ArticleDOI
Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks
TL;DR: A new approach for FPGA testing is presented that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test, without area or performance penalties to the system function implemented by the FPGa.
Proceedings ArticleDOI
Using ILA testing for BIST in FPGAs
TL;DR: In this paper, an improved Built-In Self-Test (BIST) approach for the programmable logic blocks (PLBs) of a Field Programmable Gate Array (FPGA), which repeatedly reconfigures the FPGA as a group of C-testable iterative logic arrays.
Built-In Self-Test of Logic Blocks in FPGAs
TL;DR: A new approach for Field Programmable Gate Array (FPGA) testing is presented that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test, and is applicable to all levels of testing, achieves maximal fault coverage, and all tests are applied at-speed.
(Finally, A Free Lunch: BIST Without Overhead!)
TL;DR: A new approach for Field Programma- ble Gate Array (FPGA) testing is presented that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test, without any area overhead or performance penalties to the system function implemented by the FPGA.