Open Access
Built-In Self-Test of Logic Blocks in FPGAs
TLDR
A new approach for Field Programmable Gate Array (FPGA) testing is presented that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test, and is applicable to all levels of testing, achieves maximal fault coverage, and all tests are applied at-speed.Abstract:
We present a new approach for Field Programmable Gate Array (FPGA) testing that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test. As a result, BIST is achieved without any area overhead or performance penalties to the system function implemented by the FPGA. Our approach is applicable to all levels of testing, achieves maximal fault coverage, and all tests are applied at-speed. We describe the BIST architecture used to test all the programmable logic blocks in an FPGA and the configurations required to implement our approach using a commercial FPGA. We also discuss implementation problems caused by CAD tool limitations and limited architectural resources, and we describe techniques which overcolme these limitations.’read more
Citations
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Proceedings ArticleDOI
Fault tolerant methods for reliability in FPGAs
TL;DR: This paper provides the first comprehensive survey of fault detection methods and fault tolerance schemes specifically for FPGAs, with the goal of laying a strong foundation for future research in this field.
Proceedings ArticleDOI
Built-In Self-Test of configurable logic blocks in Virtex-5 FPGAs
TL;DR: A Built-In Self-Test (BIST) approach is presented for the configurable logic blocks (CLBs) in Xilinx Virtex-5 Field Programmable Gate Arrays (FPGAs) and a novel output response analyzer (ORA) design provides both an overall single-bit pass/fail result and optimal diagnostic resolution when faults are detected.
Proceedings ArticleDOI
SEU mitigation for sram-based fpgas through dynamic partial reconfiguration
TL;DR: A methodology for designing reliable systems implemented on Field Programmable Gate Arrays (FPGAs), able to cope with the effects of Single Event Upset (SEU) faults, causing bit-flips in SRAM memory is presented.
Journal ArticleDOI
Fault-Resilient Lightweight Cryptographic Block Ciphers for Secure Embedded Systems
TL;DR: Error detection schemes for lightweight block ciphers are proposed with the case study of XTEA (eXtended TEA), and can be applied to lightweight hash functions with similar structures, making the presented schemes suitable for providing reliability to their lightweight security-constrained hardware implementations.
Proceedings ArticleDOI
A multi-configuration strategy for an application dependent testing of FPGAs
TL;DR: An application-dependent test strategy to be used by an FPGA user is presented which requires only 3 test configurations and the used logic blocks are fully tested by modifying the interconnect configuration.
References
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Book
Testing Semiconductor Memories: Theory and Practice
TL;DR: Memory modeling functional testing: reduced functional RAM chip model Functional RAM chip testing functional ROM chip testingfunctional memory array testing functional memory board testing electrical testing: parametric testing dynamic testing on chip testing conclusions: address line scrambling various proofs software package.
Journal ArticleDOI
Verification Testing—A Pseudoexhaustive Test Technique
TL;DR: A new approach to test pattern generation which is particularly suitable for self-test is described, which requires much less computation time and fault coverage is much higher—all irredundant multiple as well as single stuck faults are detected.
Proceedings ArticleDOI
Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks
TL;DR: A new approach for FPGA testing is presented that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test, without area or performance penalties to the system function implemented by the FPGa.