Proceedings ArticleDOI
Using ILA testing for BIST in FPGAs
Charles E. Stroud,E. Lee,Srinivasa Konala,Miron Abramovici +3 more
- pp 68-75
TLDR
In this paper, an improved Built-In Self-Test (BIST) approach for the programmable logic blocks (PLBs) of a Field Programmable Gate Array (FPGA), which repeatedly reconfigures the FPGA as a group of C-testable iterative logic arrays.Abstract:
We present an improved Built-In Self-Test (BIST) approach for the programmable logic blocks (PLBs) of a Field Programmable Gate Array (FPGA), which repeatedly reconfigures the FPGA as a group of C-testable iterative logic arrays. The new architecture is easily scalable with increasing size of FPGAs and ensures routability of the various configurations required to completely test the FPGA in three test sessions. In addition, the BIST approach addresses RAM mode testing as well as testing the adder/subtractor modes in FPGAs.read more
Citations
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Proceedings ArticleDOI
Built-in self-test of FPGA interconnect
TL;DR: The first BIST approach for testing the programmable routing network in FPGAs is introduced, which detects opens in, and shorts among, wiring segments, and also faults affecting theprogrammable switches that configure the FPGA interconnect.
Journal ArticleDOI
BIST-based test and diagnosis of FPGA logic blocks
TL;DR: In this article, the authors present a built-in self-test (BIST) approach able to diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution.
Proceedings ArticleDOI
BIST-based diagnostics of FPGA logic blocks
TL;DR: This paper presents the first approach able to diagnose faulty programmable logic blocks (PLBs) in Field Programmable Gate Arrays (FPGAs) with maximal diagnostic resolution, based on a new Built-In Self-Test (BIST) architecture for FPGAs and can accurately locate any single and most multiple faulty PLBs.
Journal ArticleDOI
Testing configurable LUT-based FPGA's
TL;DR: It is shown that different arrangements of disjoint one-dimensional cell arrays with cascaded horizontal connections and common vertical input lines provide a good logic testing regimen and new conditions for C-testability of programmable/reconfigurable arrays are defined.
Patent
Method and apparatus for testing field programmable gate arrays
Abstract: A method of built-in self-testing field programmable gate arrays (FPGAs) including the programmable logic blocks, the programmable routing networks and the programmable input/output cells or boundary ports at the device, board or system level includes testing the programmable logic blocks, reconfiguring a first group of he programmable logic blocks to include a test pattern generator and an output response analyzer, and configuring the programmable routing network into groups of wires under test. This step is followed by generating test patterns propagated along the wires under test and comparing the outputs utilizing the output response analyzer. Based on the result of the comparison a pass/fail test result indication is routed to the associated boundary port. The results from a plurality of output response analyzers can be compared utilizing an iterative comparator in order to reduce the number of boundary ports required during testing.
References
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Journal ArticleDOI
Easily Testable Iterative Systems
TL;DR: Property of systems that enable them to be tested with a fixed constant number of tests independent of p, the number of cells in the system are considered, referred to as C-testable.
Journal ArticleDOI
Verification Testing—A Pseudoexhaustive Test Technique
TL;DR: A new approach to test pattern generation which is particularly suitable for self-test is described, which requires much less computation time and fault coverage is much higher—all irredundant multiple as well as single stuck faults are detected.
Proceedings ArticleDOI
Testing for faults in combinational cellular logic arrays
TL;DR: This paper confirms that the iterative structure and the short intercell connections of a cellular logic array would allow it to be tested from its edge terminals much more easily than a relatively disorganized interconnection of the same number of gates, and describes procedures for deriving minimal (or near-minimal) schedules of test inputs, to be applied to a combinational cellular array in order to detect the presence of any single faulty cell.
Proceedings ArticleDOI
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)
TL;DR: A new approach for Field Programmable Gate Array (FPGA) testing is presented that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test, achieving BIST without any area overhead or performance penalties to the system function implemented by the FPGA.
Proceedings ArticleDOI
An approach for testing programmable/configurable field programmable gate arrays
W.K. Huang,Fabrizio Lombardi +1 more
TL;DR: This paper presents a new general technique for testing field programmable gate arrays (FPGAs) by fully exploiting their programmable and configurable characteristics by introducing a hybrid fault model based on a physical and behavioral characterization.