As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50–70% when compared to IMPLY, NAND, NOR and other similar logic primitives.

https://www.mdpi.com/2079-9268/10/3/28/pdf

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

To overcome the “von Neumann bottleneck,” methods to compute in memory are being researched in many emerging memory technologies, including resistive RAMs (ReRAMs). Majority logic is efficient for synthesizing arithmetic circuits when compared to NAND/NOR/IMPLY logic. In this work, we propose a method to implement a majority gate in a transistor-accessed ReRAM array during the READ operation. Together with NOT gate, which is also implemented in memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. While many methods have been proposed recently to implement the Boolean logic in memory, the latency of in-memory adders implemented as a sequence of such Boolean operations is exorbitant ( ${O}$ ( ${n}$ )). Parallel-prefix (PP) adders use prefix computation to accelerate addition in conventional CMOS-based adders. By exploiting the parallel-friendly nature of the proposed majority gate and the regular structure of the memory array, it is demonstrated how PP adders can be implemented in memory in ${O}$ (log( ${n}$ )) latency. The proposed in-memory addition technique incurs a latency of $4\cdot $ log( ${n}$ )+6 for $n$ -bit addition and is energy-efficient due to the absence of sneak currents in 1Transistor–1Resistor configuration.

/pdf/accelerated-addition-in-resistive-ram-array-using-parallel-9hqg7b6g2x.pdf

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.

A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells

A highly accurate 3-D indoor passive localization and identification system is presented in this article. The system can monitor various commercial Wi-Fi devices through the proposed received signal strength indicator (RSSI)-based angle of arrival (AoA) estimation technique. RSSI-based localization systems conventionally use additional assistance techniques, such as distance–RSSI calibration, fingerprint analysis, machine learning, and a widespread setup to achieve high accuracy. On the contrary, this proposed system can operate in complex environments full of scattering objects and obstructions without requiring any additional assistance techniques. The proposed technique uses a six-port network to evaluate the phase difference in the carrier waves of Wi-Fi signals without the influence of modulated signals. The network also preserves the modulated signals without the influence of the phase difference of the carrier waves such that Wi-Fi devices can be identified. Regarding practical applications, the system is designed to be capable of detecting devices through walls and thus can be hidden outside the monitored room. The experimental results indicate that in single-source localization, the average error is 0.089 m; in multiple-source localization, it is 0.354 m; and for seeing through the wall, it is 0.24 m. In the worst case scenario, the error is still smaller than 0.63 m. The accuracy in all the experimental results was found to be at the decimeter level. In summary, this study experimentally validated a 3-D indoor localization and identification system for diverse Wi-Fi devices in various environments.

3-D Indoor Localization and Identification Through RSSI-Based Angle of Arrival Estimation With Real Wi-Fi Signals

A highly accurate 3-D indoor passive localization and identification system is presented in this article. The system can monitor various commercial Wi-Fi devices through the proposed received signal strength indicator (RSSI)-based angle of arrival (AoA) estimation technique. RSSI-based localization systems conventionally use additional assistance techniques, such as distance–RSSI calibration, fingerprint analysis, machine learning, and a widespread setup to achieve high accuracy. On the contrary, this proposed system can operate in complex environments full of scattering objects and obstructions without requiring any additional assistance techniques. The proposed technique uses a six-port network to evaluate the phase difference in the carrier waves of Wi-Fi signals without the influence of modulated signals. The network also preserves the modulated signals without the influence of the phase difference of the carrier waves such that Wi-Fi devices can be identified. Regarding practical applications, the system is designed to be capable of detecting devices through walls and thus can be hidden outside the monitored room. The experimental results indicate that in single-source localization, the average error is 0.089 m; in multiple-source localization, it is 0.354 m; and for seeing through the wall, it is 0.24 m. In the worst case scenario, the error is still smaller than 0.63 m. The accuracy in all the experimental results was found to be at the decimeter level. In summary, this study experimentally validated a 3-D indoor localization and identification system for diverse Wi-Fi devices in various environments. 

Efforts to combat the ‘von Neumann bottleneck’ have been strengthened by Resistive RAMs (RRAMs), which enable computation in the memory array. Majority logic can accelerate computation when compared to NAND/NOR/IMPLY logic due to it’s expressive power. In this work, we propose a method to compute majority while reading from a transistor-accessed RRAM array. The proposed gate was verified by simulations using a physics-based model (for RRAM) and industry standard model (for CMOS sense amplifier) and, found to tolerate reasonable variations in the RRAMs’ resistive states. Together with NOT gate, which is also implemented in-memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. The parallel-friendly nature of the proposed gate is exploited to implement an eight-bit parallel-prefix adder in memory array. The proposed in-memory adder could achieve a latency reduction of 70% and 50% when compared to IMPLY and NAND/NOR logic-based adders, respectively.

/pdf/a-parallel-friendly-majority-gate-to-accelerate-in-memory-1vm6d73bvx.pdf

A Parallel-friendly Majority Gate to Accelerate In-memory Computation

In this paper, a scalable, fully digital adjustable, bistatic 60 GHz MIMO six-port transceiver is presented. The circuit features four independent transmitters and four six-port receivers on a single chip. The reference clock frequency of 15 GHz is buffered and multiplied up to 60 GHz. The reference clock is also amplified and feed to an output port of the chip to render possible cascading multiple chips for massive MIMO applications. The receivers each include a VGA to set the reference power level, a LNA for amplification of the weak antenna signal and the six-port structure with three broadside linecoupler, a wilkinson-divider and four power detectors. The transmitters each include a switched-line phase shifter and a power amplifier. The chip has a size of 4 mm x 3.1 mm and a power consumption of 960 mW from a 3.3 V power supply. A minimum input power of -22 dBm is needed at the input clock. The transmitters deliver a maximum output power of 9.1 dBm at 60 GHz. The phase is adjustable in a range from 0° to 325.4°. The successful measurement results indicate, that the MIMO six-port transceiver is well suited for radar applications.

An Integrated Bistatic 4TX/4RX Six-Port MIMO-Transceiver at 60 GHz in a 130-nm SiGe BiCMOS Technology for Radar Applications

Pattern recognition as a computing task is very well suited for machine learning algorithms utilizing artificial neural networks (ANNs). Computing systems using ANNs usually require some sort of data storage to store the weights and bias values for the processing elements of the individual neurons. This paper introduces a memory block using resistive memory cells (RRAM) to realize this weight and bias storage in an embedded and distributed way while also offering programming and multi-level ability. By implementing power gating, overall power consumption is decreased significantly without data loss by taking advantage of the non-volatility of the RRAM technology. Due to the versatility of the peripheral circuitry, the presented memory concept can be adapted to different applications and RRAM technologies.

/pdf/a-low-power-rram-memory-block-for-embedded-multi-level-4hq5l6c61l.pdf

Stefan Pechmann

Papers

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells

A Parallel-friendly Majority Gate to Accelerate In-memory Computation

An Integrated Bistatic 4TX/4RX Six-Port MIMO-Transceiver at 60 GHz in a 130-nm SiGe BiCMOS Technology for Radar Applications

A Low-Power RRAM Memory Block for Embedded, Multi-Level Weight and Bias Storage in Artificial Neural Networks