S
Stephen A. Edwards
Researcher at Columbia University
Publications - 142
Citations - 4736
Stephen A. Edwards is an academic researcher from Columbia University. The author has contributed to research in topics: Concurrency & Compiler. The author has an hindex of 28, co-authored 134 publications receiving 4583 citations. Previous affiliations of Stephen A. Edwards include University of California & University of Amsterdam.
Papers
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Journal ArticleDOI
The synchronous languages 12 years later
Albert Benveniste,Paul Caspi,Stephen A. Edwards,Nicolas Halbwachs,P. Le Guernic,R. de Simone +5 more
TL;DR: The improvements, difficulties, and successes that have occured with the synchronous languages since then are discussed.
Book ChapterDOI
VIS: A System for Verification and Synthesis
Robert K. Brayton,Gary D. Hachtel,Alberto Sangiovanni-Vincentelli,Fabio Somenzi,Adnan Aziz,Szu-Tsung Cheng,Stephen A. Edwards,Sunil P. Khatri,Yuji Kukimoto,Abelardo Pardo,Shaz Qadeer,Rajeev Kumar Ranjan,Shaker Sarwary,Thomas R. Shiple,Gitanjali Swamy,Tiziano Villa +15 more
TL;DR: VIS provides the capability to check the combinational equivalence of two designs and provides traditional verification in the form of a cycle-based simulator that uses BDD techniques.
Journal ArticleDOI
Design of embedded systems: formal models, validation, and synthesis
TL;DR: This paper addresses the design of reactive real-time embedded systems by reviewing the variety of approaches to solving the specification, validation, and synthesis problems for such embedded systems.
Proceedings ArticleDOI
The case for the precision timed (PRET) machine
Stephen A. Edwards,Edward A. Lee +1 more
TL;DR: It is time for a new era of processors whose temporal behavior is as easily controlled as their logical function, and these machines are called precision timed (PRET) machines.
Proceedings ArticleDOI
Predictable programming on a precision timed architecture
TL;DR: A SPARC-based processor with predictable timing and instruction-set extensions that provide precise timing control is described, and the effectiveness of this precision-timed (PRET) architecture is demonstrated through example applications running in simulation.