Steve Dai

TL;DR: MAGNet, a modular accelerator generator for neural networks, is proposed and an inference accelerator optimized for image classification application using three different neural networks—AlexNet, ResNet, and DriveNet is designed.

TL;DR: Rosetta is a realistic benchmark suite for software programmable FPGAs that can be useful for the HLS research community, but can also serve as a set of design tutorials for non-expert HLS users.

TL;DR: This work builds a large collection of C-to-FPGA results from a diverse set of realistic HLS applications and identifies relevant features from HLS reports for estimating post-implementation metrics, and trains and compares a number of promising machine learning models to effectively and efficiently bridge the accuracy gap.

TL;DR: The Celerity 16-nm open-source SoC was implemented in nine months using an architectural trifecta to minimize development time: a general-purpose tier, a massively parallel tier comprised of a RISC-V tiled manycore array, and a specialization tier that uses high-level synthesis to create an algorithmic neural-network accelerator.

TL;DR: ElasticFlow is proposed, a novel architectural synthesis approach capable of dynamically distributing inner loops to an array of loop processing units (LPUs) in a complexity-effective manner that demonstrates significant performance improvements over a widely used commercial HLS tool for Xilinx FPGAs.