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Sunao Aya

Researcher at Mitsubishi Electric

Publications -  33
Citations -  320

Sunao Aya is an academic researcher from Mitsubishi Electric. The author has contributed to research in topics: Resist & Lithography. The author has an hindex of 11, co-authored 33 publications receiving 315 citations. Previous affiliations of Sunao Aya include Mitsubishi Corporation.

Papers
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Journal ArticleDOI

Sub-hundred nanometre pitch measurements using an AFM with differential laser interferometers for designing usable lateral scales

TL;DR: In this paper, the authors developed a new atomic force microscope with differential laser interferometers (DLI-AFM), carried out test measurements of the prototype 1D-grating standards with pitches of 100, 80, 60 and 50 nm using the DLI-AAFM and evaluated the uncertainty in the pitch measurements.
Journal ArticleDOI

Magnetization chirality due to asymmetrical structure in Ni-Fe annular dots for high-density memory cells

TL;DR: In this paper, Ni-Fe asymmetric ring dots with partially planed outer sides were investigated as candidates for high-density magnetic memory cells, and the magnetic states were measured with magnetic force microscopy.
Journal ArticleDOI

Validity of double and triple Gaussian functions for proximity effect correction in X-ray mask writing

TL;DR: In this paper, an improved function was proposed to express the deposited energy intensity distribution for fine patterns or that for heavy metals such as X-ray absorbers, and an experimental method was also proposed for obtaining the function parameters, and the optimal parameters were obtained for Si and W-Ti substrates at acceleration voltage of 25 kV.
Journal ArticleDOI

Magnetically pinned ring dots for spin valve or magnetic tunnel junction memory cells

TL;DR: In this paper, the Ni-Fe/Mn-Ir asymmetric ring dots with partially planed outer sides are investigated in order to confirm a method for obtaining pinned layers in magnetic memories with asymmetric round shapes.
Patent

Semiconductor device and method for manufacturing semiconductor device

TL;DR: In this article, a semiconductor device capable of suppressing time variation of a threshold voltage and a method of manufacturing the same is presented, which comprises a drift layer formed on a polysilicon substrate, first well regions formed in a surface layer of the drift layer, being apart from one another, a gate insulating film formed, extending on the drift layers and each of the first well region, a gated electrode selectively formed on the gate's surface, a source contact hole penetrating through the gate-insulating film and reaching the inside of each well regions, and a residual