S
Sunil V. Hattangady
Researcher at Texas Instruments
Publications - 31
Citations - 1582
Sunil V. Hattangady is an academic researcher from Texas Instruments. The author has contributed to research in topics: Gate oxide & Layer (electronics). The author has an hindex of 23, co-authored 31 publications receiving 1556 citations.
Papers
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Journal ArticleDOI
Security in embedded systems: Design challenges
TL;DR: An introduction to the challenges involved in secure embedded system design is provided, recent advances in addressing them are discussed, and opportunities for future research are identified.
Proceedings ArticleDOI
CMOS metal replacement gate transistors using tantalum pentoxide gate insulator
Amitava Chatterjee,Richard A. Chapman,Keith A. Joyner,M. Otobe,Sunil V. Hattangady,M. J. Bevan,George A. Brown,H. Yang,Q. He,D. Rogers,S.J. Fang,Robert Kraft,Antonio L. P. Rotondaro,M. Terry,K. Brennan,S. Aur,J.C. Hu,H.-L. Tsai,P.J. Jones,G. Wilk,M. Aoki,Mark S. Rodder,Ih-Chin Chen +22 more
TL;DR: In this paper, a full CMOS process using a combination of a TiN/W Metal Replacement Gate Transistor design with a high dielectric constant gate insulator of tantalum pentoxide over thin remote plasma nitrided gate oxide was reported.
Patent
Method of forming thin silicon nitride or silicon oxynitride gate dielectrics
TL;DR: In this paper, an embodiment of the instant invention is presented for forming a dielectric layer, the method comprising the steps of: providing a semiconductor substrate (substrate 12), the substrate having a surface, forming an oxygen-containing layer (layer 14), subjecting the oxygencontaining layer to a nitrogen containing plasma (plasma 16) so that the nitrogen is either incorporated into the oxygen containing layer (see regions 18, 19, and 20) or forms a nitride layer at the surface of the substrate (region 22).
Patent
Method of forming multiple gate oxide thicknesses using high density plasma nitridation
TL;DR: In this paper, a high density plasma is used for selective plasma nitridation to reduce the effective gate dielectric thickness in selected areas only, and a pattern is then placed that exposes areas where a thinner effective gate oxide is desired.
Proceedings ArticleDOI
Low voltage stress-induced-leakage-current in ultrathin gate oxides
P.E. Nicollian,Mark S. Rodder,Douglas T. Grider,P. Chen,Robert M. Wallace,Sunil V. Hattangady +5 more
TL;DR: In this paper, the authors show that for oxides less than /spl sim/3.5 nm, interfacial traps generated from direct tunneling stress result in a sense voltage dependent SILC mechanism that can dominate the gate leakage current at low operating voltages.