An interactive display table has a display surface for displaying images and upon or adjacent to which various objects, including a user's hand(s) and finger(s) can be detected. A video camera within the interactive display table responds to infrared (IR) light reflected from the objects to detect any connected components. Connected component correspond to portions of the object(s) that are either in contact, or proximate the display surface. Using these connected components, the interactive display table senses and infers natural hand or finger positions, or movement of an object, to detect gestures. Specific gestures are used to execute applications, carryout functions in an application, create a virtual object, or do other interactions, each of which is associated with a different gesture. A gesture can be a static pose, or a more complex configuration, and/or movement made with one or both hands or other objects.

Recognizing gestures and using gestures for interacting with software applications

An electronic device with a display and a fingerprint sensor may authenticate a user for a respective function. While a respective function of the device is in a locked state, the device displays a graphical element on the display, the graphical element indicating a first direction of finger movement that enables unlocking of the respective function. While displaying the graphical element, the device detects an input that includes movement of a finger in the first direction over the fingerprint sensor and determines whether the input meets unlock criteria based at least in part on fingerprint information of the finger detected by the fingerprint sensor during the input. In accordance with a determination that the input meets the unlock criteria, the device unlocks the respective function; and in accordance with a determination that the input does not meet the unlock criteria, the device maintains the respective function in the locked state.

Embedded authentication systems in an electronic device

An electronic device with a display and a fingerprint sensor displays a fingerprint enrollment interface and detects, on the fingerprint sensor, a plurality of finger gestures performed with a finger. The device collects fingerprint information from the plurality of finger gestures performed with the finger. After collecting the fingerprint information, the device determines whether the collected fingerprint information is sufficient to enroll a fingerprint of the finger. When the collected fingerprint information for the finger is sufficient to enroll the fingerprint of the finger, the device enrolls the fingerprint of the finger with the device. When the collected fingerprint information for the finger is not sufficient to enroll the fingerprint of the finger, the device displays a message in the fingerprint enrollment interface prompting a user to perform one or more additional finger gestures on the fingerprint sensor with the finger.

Device, method, and graphical user interface for manipulating user interfaces based on fingerprint sensor inputs

This paper examines the apparent limits, possible extensions, and applications of CMOS technology in the nanometer regime. Starting from device scaling theory and current industry projections, we analyze the achievable performance and possible limits of CMOS technology from the point of view of device physics, device technology, and power consumption. Various possible extensions to the basic logic and memory devices are reviewed, with emphasis on novel devices that are structurally distinct front conventional bulk CMOS logic and memory devices. Possible applications of nanoscale CMOS are examined, with a view to better defining the likely capabilities of future microelectronic systems. This analysis covers both data processing applications and nondata processing applications such as RF and imaging. Finally, we speculate on the future of CMOS for the coming 15-20 years.

Nanoscale CMOS

This work analyzes both by simulations and measurements the substrate crosstalk performances of various Silicon-On-Insulator (SOI) technologies, and compares them to those of normal bulk CMOS process. The influence of various parameters, such as substrate resistivity, buried oxide thickness and distance between devices, is investigated. The use of capacitive guard rings is proposed, and their effectiveness is demonstrated. A simple RC model has been developed to allow a deep understanding of these phenomena as well as to simplify future studies of more complex systems. The superiority of high-resistivity SIMOX substrates over standard SOI and bulk is finally demonstrated.

Substrate crosstalk reduction using SOI technology

Hot-carrier-induced device degradation has been studied for quarter-micrometer level buried-channel PMOSFETs. It was found that the major hot-carrier degradation mode for these small devices is quite different from that previously reported, which was caused by trapped electrons injected into the gate oxide. The new degradation mode is caused by the effect of interface traps generated by hot hole injection into the oxide near the drain in the saturation region. DC device lifetime for the new mode can be evaluated using substrate current rather than gate current as a predictor. Interface-trap generation due to hot-hole injection will become the dominant degradation mode in future PMOSFETs. >

New hot-carrier degradation mode and lifetime prediction method in quarter-micrometer PMOSFET

Copper metallization was applied to quarter-micron CMOS circuits using copper chemical vapor deposition (CVD) and chemical mechanical polishing (CMP). Both the metallization process and the electrical characteristics of CMOS devices/circuits were evaluated. Process-induced metal contamination on both sides of the wafer were quantitatively evaluated and reduced to about of 10/sup 11/ atoms/cm/sup 2/ by using an optimized cleaning sequence. The ability of borophosphosilicate-glass (BPSG) to act as a copper diffusion barrier was discovered and the ability of TiN to do so was also confirmed. Electrical characteristics of n and p MOSFET's with copper interconnections were stable even after annealing at 550/spl deg/C. The leakage current of the pn junction, capacitance-voltage characteristics and time-dependent dielectric breakdown characteristics of the MOS diode indicate that the copper metallization process did not deteriorate the pn junction and the gate oxide. Normal operation of a 53-stage quarter-micron CMOS inverter ring oscillator with copper metallization was successfully achieved.

Evaluation of a copper metallization process and the electrical characteristics of copper-interconnected quarter-micron CMOS

The fabrication of p-channel and n-channel MOSFETs with sub-quarter-micrometer n/sup +/ polysilicon gates, have been fabricated using extremely shallow source-drain (S-D) junctions, is reported p/sup +/-n junctions as shallow as 80 nm have been fabricated using preamorphization low-energy BF/sub 2/ ion implantation and rapid thermal annealing, and 80-nm n/sup +/-p junctions have been fabricated using low-energy arsenic ion implantation and rapid thermal annealing. n-channel MOSFETs with 80-mm S-D junctions and 0.16- mu m gate lengths have been fabricated, and a maximum transconductance of 400 mS/mm has been obtained. 51-stage n-channel enhancement-mode/enhancement-mode (E/E) ring oscillators and p-channel E/E ring oscillators with extremely shallow S-D junctions have also been obtained. >

Subquarter-micrometer gate-length p-channel and n-channel MOSFETs with extremely shallow source-drain junctions

A biological image correlation device includes: an image quality priority decision section (40) for evaluating image quality for each of a plurality of first image data consisting of biological images relating to the same object, according to a particular index which is in relation of a monotone function with verification accuracy of biological verification, assigning priority to each of the first image data according to the evaluation result, and outputting them; first image storage sections (6, 81) for storing the first image data to which the priority is assigned and output from the image priority decision section (40); second image storage sections (8, 61) for storing second image data used for comparison and correlation with the first image data; an image correlation section (7) for comparing and correlating the reference image data stored in the second image storage section with the first image data stored in the first image storage sections (6, 81) and outputting the comparison/correlation result; and a control section (9) for controlling the aforementioned components. The control section (9) makes the image correlation section (7) compare/correlate the second image data stored in the second image storage sections (8, 61) with the first image data stored in the first image storage sections (6, 81) according to the aforementioned priority and output the correlation result from the image correlation section (7).

Biological image correlation device and correlation method thereof

An authentication method includes the first, second, and third steps In the first step, a biometrical information sensor reads the biometrical information of a user In the second step, the read biometrical information is collated with registered biometrical information in a registration memory When the collation result represents that collation has successfully been done, user unique information from an authentication information output section is converted into an emulator signal corresponding to a service provided by a use device The emulator signal is transmitted to the use device In the third step, the use device provides the service to the user on the basis of the received emulator signal An authentication system and authentication token are also disclosed

Yukio Okazaki

Papers

New hot-carrier degradation mode and lifetime prediction method in quarter-micrometer PMOSFET

Evaluation of a copper metallization process and the electrical characteristics of copper-interconnected quarter-micron CMOS

Subquarter-micrometer gate-length p-channel and n-channel MOSFETs with extremely shallow source-drain junctions

Biological image correlation device and correlation method thereof

Authentication method, authentication system, and authentication token