The potential for collaborative, robust networks of microsensors has attracted a great deal of research attention. For the most part, this is due to the compelling applications that will be enabled once wireless microsensor networks are in place; location-sensing, environmental sensing, medical monitoring and similar applications are all gaining interest. However, wireless microsensor networks pose numerous design challenges. For applications requiring long-term, robust sensing, such as military reconnaissance, one important challenge is to design sensor networks that have long system lifetimes. This challenge is especially difficult due to the energy-constrained nature of the devices. In order to design networks that have extremely long lifetimes, we propose a physical layer driven approach to designing protocols and algorithms. We first present a hardware model for our wireless sensor node and then introduce the design of physical layer aware protocols, algorithms, and applications that minimize energy consumption of the system. Our approach prescribes methods that can be used at all levels of the hierarchy to take advantage of the underlying hardware. We also show how to reduce energy consumption of non-ideal hardware through physical layer aware algorithms and protocols.

/pdf/physical-layer-driven-protocol-and-algorithm-design-for-3uvkmg05zu.pdf

Physical layer driven protocol and algorithm design for energy-efficient wireless sensor networks

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

https://users.ece.utexas.edu/~adnan/comm-08/bluetooth-jssc-04.pdf

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

A 15-b 1-Msample/s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented. A radix 1.93, 1 b per stage design is employed. The digital self-calibration accounts for capacitor mismatch, comparator offset, charge injection, finite op-amp gain, and capacitor nonlinearity contributing to DNL. A THD of -90 dB was measured with a 9.8756-kHz sine-wave input. The DNL was measured to be within +or-0.25 LSB at 15 b, and the INL was measured to be within +or-1.25 LSB at 15 b. The die area is 9.3 mm*8.3 mm and operates on +or-4-V power supply with 1.8-W power dissipation. The ADC is fabricated in an 11-V, 4-GHz, 2.4- mu m BiCMOS process. >

A 15-b 1-Msample/s digitally self-calibrated pipeline ADC

This paper presents a low-power SoC that performs EEG acquisition and feature extraction required for continuous detection of seizure onset in epilepsy patients. The SoC corresponds to one EEG channel, and, depending on the patient, up to 18 channels may be worn to detect seizures as part of a chronic treatment system. The SoC integrates an instrumentation amplifier, ADC, and digital processor that streams features-vectors to a central device where seizure detection is performed via a machine-learning classifier. The instrumentation-amplifier uses chopper-stabilization in a topology that achieves high input-impedance and rejects large electrode-offsets while operating at 1 V; the ADC employs power-gating for low energy-per-conversion while using static-biasing for comparator precision; the EEG feature extraction processor employs low-power hardware whose parameters are determined through validation via patient data. The integration of sensing and local processing lowers system power by 14× by reducing the rate of wireless EEG data transmission. Feature vectors are derived at a rate of 0.5 Hz, and the complete one-channel SoC operates from a 1 V supply, consuming 9 ? J per feature vector.

/pdf/a-micro-power-eeg-acquisition-soc-with-integrated-feature-3tsumsfih4.pdf

A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System

Injection-locked oscillators (ILOs) are investigated in a new theoretical approach. A first-order differential equation is derived for the noise dynamics of ILOs. A single-ended injection-locked frequency divider (SILFD) is designed in a 0.5-/spl mu/m CMOS technology operating at 1.8 GHz with more than 190 MHz locking range while consuming 3 mW of power. A differential injection-locked frequency divider (DILFD) is designed in a 0.5-/spl mu/m CMOS technology operating at 3 GHz and consuming 0.45 mW, with a 190 MHz locking range. A locking range of 370 MHz is achieved for the DILFD when the power consumption is increased to 1.2 mW.

/pdf/superharmonic-injection-locked-frequency-dividers-jgrgw5ct77.pdf

Superharmonic injection-locked frequency dividers

A digital compensation method and key circuits are presented that allow fractional-N synthesizers to be modulated at data rates greatly exceeding their bandwidth. Using this technique, a 1.8-GHz transmitter capable of digital frequency modulation at 2.5 Mb/s can be achieved with only two components: a frequency synthesizer and a digital transmit filter. A prototype transmitter was constructed to provide proof of concept of the method; its primary component is a custom fractional-N synthesizer fabricated in a 0.6-/spl mu/m CMOS process that consumes 27 mW. Key circuits on the custom IC are an on-chip loop filter that requires no tuning or external components, a digital MASH /spl Sigma/-/spl Delta/ modulator that achieves low power operation through pipelining, and an asynchronous, 64-modulus divider (prescaler). Measurements from the prototype indicate that it meets performance requirements of the digital enhanced cordless telecommunications (DECT) standard.

/pdf/a-27-mw-cmos-fractional-n-synthesizer-using-digital-4raqamn9c1.pdf

A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation

MOSFETs subjected to large-signal gate-source voltage pulses on microsecond to millisecond time scales exhibit transient threshold voltage shifts which relax over considerably longer periods of time. This problem is important in high-accuracy analog circuits where it can cause errors at the 12 b level and above. In this paper, transient threshold voltage shifts are characterized with respect to their dependence on stress amplitude and duration, relaxation time, gate bias, substrate bias, drain voltage, temperature, and channel width and length. In contrast to previous studies, threshold voltage shifts are measured at time and voltage scales relevant to analog circuits, and are shown to occur even when the effects of Fowler-Nordheim tunneling, avalanche injection, hot carriers, trap generation, self-heating, mobile ions, and dipolar polarizations are absent. A new model is proposed in which channel charge carriers tunnel to and from near-interface oxide traps by one of three parallel pathways. Transitions may occur elastically, by direct tunneling between the silicon band edges and an oxide trap, or inelastically, by tunneling in conjunction with a thermal transition in the insulator or at the Si-SiO/sub 2/ interface. Simulations based on this model show excellent agreement with experimental results. The threshold voltage shifts are also shown to be correlated with 1/f noise, in corroboration of the tunneling model. Techniques for the minimization and modeling of errors in circuits are presented. >

Characterization, modeling, and minimization of transient threshold voltage shifts in MOSFETs

A 18GHz transmitter supports a data rate of 25Mb/s using GFSK with BT=05, the same modulation method used in DECT The architecture increases, by over an order of magnitude, the achievable data rate for the transmitter method, in which phase/frequency modulation is by dithering the divide value within a phase locked loop (PLL) This design avoids mixers and D/A converters to generate I and Q waveforms, so that simplicity and power savings are achieved The system was built using a custom, CMOS fractional-N synthesizer that contains several key circuits Included are an on-chip, continuous-time filter that requires no tuning or external components, a digital MASH /spl Sigma//spl delta/ converter that achieves low-power operation through pipelining, and a 64-modulus divider that supports any divide value between 32 and 635 in half cycle increments Also included is a phase/frequency detector (PFD) that avoids dead-zone problems

http://ieeexplore.ieee.org/iel3/4459/12641/00585430.pdf

A 27 mW CMOS fractional-N synthesizer/modulator IC

Hysteresis in the threshold voltage of MOSFETs due to oxide traps is discussed, which can impose serious limitations on the accuracy and speed of analog circuits. The measured magnitude of the input-referred hysteresis ranges from 100 mu V to more than 1 mV in NMOS devices stressed with positive gate-source voltages ranging from 1 to 5 V on microsecond-to-millisecond time scales. This hysteresis is explained by a model in which electrons tunnel to oxide traps close to the interface. >

T.L. Tewksbury

Papers

A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation

Characterization, modeling, and minimization of transient threshold voltage shifts in MOSFETs

A 27 mW CMOS fractional-N synthesizer/modulator IC

The effects of oxide traps on the large-signal transient response of analog MOS circuits