A 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor-control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitor-free operation. The proposed LDO has been implemented in a commercial 0.6-/spl mu/m CMOS technology, and the active chip area is 568 /spl mu/m/spl times/541 /spl mu/m. The total error of the output voltage due to line and load variations is less than /spl plusmn/0.25%, and the temperature coefficient is 38 ppm//spl deg/C. Moreover, the output voltage can recover within 2 /spl mu/s for full load-current changes. The power-supply rejection ratio at 1 MHz is -30 dB, and the output noise spectral densities at 100 Hz and 100 kHz are 1.8 and 0.38 /spl mu/V//spl radic/Hz, respectively.

A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation

A sub-1-V CMOS bandgap voltage reference requiring no low threshold voltage device is introduced in this paper. In a CMOS technology with V/sub thn/ /spl ap/ |V/sub thp/| /spl ap/ 0.9 V at 0/spl deg/C, the minimum supply voltage of the proposed voltage reference is 0.98 V, and the maximum supply current is 18 /spl mu/A. A temperature coefficient of 15 ppm//spl deg/C from 0/spl deg/C to 100/spl deg/C is recorded after trimming. The active area of the circuit is about 0.24 mm/sup 2/.

A sub-1-V 15-ppm//spl deg/C CMOS bandgap voltage reference without requiring low threshold voltage device

We present a bandgap circuit capable of generating a reference voltage of 0.53 V. The circuit, implemented In a submicron BiCMOS technology, operates with a supply voltage of 1 V, consuming 92 /spl mu/W at room temperature. In the bandgap circuit proposed, we use a nonconventional operational amplifier which achieves virtually zero systematic offset, operating directly from the 1-V power supply. The bandgap architecture used allows a straightforward implementation of the curvature compensation method. The proposed circuit achieves 7.5 ppm/K of temperature coefficient and 212 ppm/V of supply voltage dependence, without requiring additional operational amplifiers or complex circuits for the curvature compensation.

/pdf/curvature-compensated-bicmos-bandgap-with-1-v-supply-voltage-2g1t6by4d8.pdf

Curvature-compensated BiCMOS bandgap with 1-V supply voltage

A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

A low-power CMOS voltage reference was developed using a 0.35 mum standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, which was about 745 mV for the MOSFETs we used. The temperature coefficient of the voltage was 7 ppm/degC at best and 15 ppm/degC on average, in a range from - 20 to 80degC. The line sensitivity was 20 ppm/V in a supply voltage range of 1.4-3 V, and the power supply rejection ratio (PSRR) was -45 dB at 100 Hz. The power dissipation was 0.3 muW at 80degC. The chip area was 0.05 mm2 . Our device would be suitable for use in subthreshold-operated, power-aware LSIs.

/pdf/a-300-nw-15-ppm-circ-c-20-ppm-v-cmos-voltage-reference-5c6xnvq0l1.pdf

A 300 nW, 15 ppm/ $^{\circ}$ C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs

This paper proposes a CMOS bandgap reference (BGR) circuit, which can successfully operate with sub-1-V supply, In the conventional BGR circuit, the output voltage V/sub ref/ is the sum of the built-in voltage of the diode V/sub f/ and the thermal voltage V/sub T/ of kT/q multiplied by a constant. Therefore, V/sub ref/ is about 1.25 V, which limits a low supply-voltage operation below 1 V. Conversely, in the proposed BGR circuit, V/sub ref/ has been converted from the sum of two currents; one is proportional to V/sub f/ and the other is proportional to V/sub T/. An experimental BGR circuit, which is simply composed of a CMOS op-amp, diodes, and resistors, has been fabricated in a conventional 0.4-/spl mu/m flash memory process. Measured V/sub ref/ is 518/spl plusmn/15 mV (3/spl sigma/) for 23 samples on the same wafer at 27-125/spl deg/C.

/pdf/a-cmos-bandgap-reference-circuit-with-sub-1-v-operation-19ry3iexxl.pdf

A CMOS bandgap reference circuit with sub-1-V operation

This paper proposes a CMOS band-gap reference (BGR) circuit, which can successfully operate with sub-1 V. In the conventional BGR circuit, the output voltage, Vref, is the sum of the built-in voltage of the diode, Vf, and the thermal voltage, VT, of kT/q multiplied by a constant. Thereby, Vref is about 1.25 V, which limits a low Vcc operation below 1 V. Conversely, in the proposed BGR circuit, Vref has been converted from the sum of two currents; one is proportional to Vf; and the other is proportional to VT. An experimental BGR circuit, which is simply composed of a CMOS opamp, diodes, and resistors, has been fabricated in a conventional double metal 0.4 /spl mu/m process. Measured Vref is 515 mV/spl plusmn/15 mV (3 /spl sigma/) for 23 samples on the same wafer at 27/spl deg/C through 125/spl deg/C.

/pdf/a-cmos-band-gap-reference-circuit-with-sub-1-v-operation-1qcprb4351.pdf

A CMOS band-gap reference circuit with sub 1 V operation

There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.

Boosted voltage generating circuit and semiconductor memory device having the same

A 1.8-V-only 32-Mb NOR flash EEPROM has been developed based on the 0.25-/spl mu/m triple-well double-metal CMOS process. A channel-erasing scheme has been implemented to realize a cell size of 0.49 /spl mu/m/sup 2/, the smallest yet reported for 0.25-/spl mu/m CMOS technology. A block decoder circuit with a novel erase-reset sequence has been designed for the channel-erasing operation. A bitline direct sensing scheme and a wordline boosted voltage pooling method have been developed to obtain high-speed reading operation at low voltage. An access time of 90 ns at 1.8 V has been realized.

A channel-erasing 1.8 V-only 32 Mb NOR flash EEPROM with a bit-line direct-sensing scheme

A low-power wordline voltage generating system is developed for low-voltage flash memories. The limit for the stand-by current including the operation current for the band-gap reference and the stand-by wordline voltage generator is discussed. The system was implemented on a 1.8-V 32-Mb flash memory fabricated with a 0.25-/spl mu/m flash memory process and achieved with very low stand-by current of 2 /spl mu/A typically, and high operating frequency of 25 MHz in read operation at 1.8 V. A low-voltage level shifter with high-speed switching is also proposed.

T. Miyaba

Papers

A CMOS bandgap reference circuit with sub-1-V operation

A CMOS band-gap reference circuit with sub 1 V operation

Boosted voltage generating circuit and semiconductor memory device having the same

A channel-erasing 1.8 V-only 32 Mb NOR flash EEPROM with a bit-line direct-sensing scheme

Wordline voltage generating system for low-power low-voltage flash memories