Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. This paper provides the basic reversible logic gates, which in designing of more complex system having reversible circuits as a primitive component and which can execute more complicated operations using quantum computers. The reversible circuits form the basic building block of quantum computers as all quantum operations are reversible. This paper presents the data relating to the primitive reversible gates which are available in literature and helps researches in designing higher complex computing circuits using reversible gates.

A Review on Reversible Logic Gates and their Implementation

Multipliers are vital components of any processor or computing machine. More often than not, performance of microcontrollers and Digital signal processors are evaluated on the basis of number of multiplications performed in unit time. Hence better multiplier architectures are bound to increase the efficiency of the system. Vedic multiplier is one such promising solution. Its simple architecture coupled with increased speed forms an unparalleled combination for serving any complex multiplication computations. Tagged with these highlights, implementing this with reversible logic further reduces power dissipation. Power dissipation is another important constraint in an embedded system which cannot be neglected. In this paper we bring out a Vedic multiplier known as “Urdhva Tiryakbhayam” meaning vertical and crosswise, implemented using reversible logic, which is the first of its kind. This multiplier may find applications in Fast Fourier Transforms (FFTs), and other applications of DSP like imaging, software defined radios, wireless communications.

Design of high speed low power multiplier using Reversible logic: A Vedic mathematical approach

One of the most promising solutions for replacing present technologies is Quantum Cellular Automata (QCA) technology Considering its nature, this technology has very low energy losses On the other hand, designing circuits that are without waste of information or reversible can be useful for decreasing energy losses The arithmetic logic unit (ALU) is recognized as the basis of processor systems In this paper, a reversible ALU is proposed along with its implementation and simulation QCA cells that benefit from a new reversible gate that we call NHG (Naghibzadeh---Hoshmand Gate) The proposed NHG gate has better performance in terms of cost and delay when compared with similar gates Thus, the ALU shows acceptable improvement in measures used to evaluate reversible circuits and circuits implemented with QCA cells when compared with previous works

Design and simulation of a reversible ALU by using QCA cells with the aim of improving evaluation parameters

Multiplier design is always a challenging task; how many ever novel designs are proposed, the user needs demands much more optimized ones. Vedic mathematics is world renowned for its algorithms that yield quicker results, be it for mental calculations or hardware design. Power dissipation is drastically reduced by the use of Reversible logic. The reversible Urdhva Tiryakbhayam Vedic multiplier is one such multiplier which is effective both in terms of speed and power. In this paper we aim to enhance the performance of the previous design. The Total Reversible Logic Implementation Cost (TRLIC) is used as an aid to evaluate the proposed design. This multiplier can be efficiently adopted in designing Fast Fourier Transforms (FFTs) Filters and other applications of DSP like imaging, software defined radios, wireless communications.

Optimized reversible vedic multipliers for high speed low power operations

In this work, we are integrating thermal aware design approach in energy efficient Vedic multiplier on FPGA. In the beginning of this universe, Veda describes heat receiving from the Sun god as Suryamrit (Surya i.e. Sun +Amrit i.e. Nectar= Suryamrit i.e. Nectar coming from the Sun God). Now, whole world is feeling anxious about temperature. How our thinking pattern is changing with evolution of mankind? This paper deals with that question and the whole work is going in direction to get solution of this problem with mechanism of ambient (room) temperature scaling and energy efficient LVCMOS I/O standard. LVCMOS is an acronym for low voltage complementary metal oxide semiconductor. In this Vedic multiplier, we are using three LVCMOS I/O standard. LVCMOS12 is available only in 65nm and 40nm FPGA. Rest LVCMOS18 and LVCMOS25 is available among 40nm, 65nm and 90nm FPGA. In order to test the thermal sustainability of our Vedic multiplier, we are testing it in three different room temperature 20°C, 30°C, and 40°C. Using LVCMOS25, there is 12.99%, 19.23% and 10.28% reduction in power dissipation on 90nm, 65nm and 40nm respectively. For LVCMOS25, when our Vedic multiplier design is migrated from 40nm design to 90nm design, there is 87.72% reduction in power dissipation of Vedic multiplier when temperature is constant 20°C.

LVCMOS Based Thermal Aware Energy Efficient Vedic Multiplier Design on FPGA

Quantum computing is one of the emerging fields of technology that has been a guiding light for low power VLSI, low power CMOS design, optical information computing, DNAcomputing, Bio-informatics and Nano-technology .A quantum circuit is a model for quantum computation in which a computation is performed by a sequence of quantum gates, which are reversible transformation on a quantum mechanical analog of an n bit register, referred to as an n- qubit. Code converters are required day in and day out. In this paper, a reversible 5421 to binary code converter is implemented.

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Novel Code Converter Employing Reversible Logic

Power dissipation is an important design criterion during the VLSI process flow. Reversible logic is one of the promising fields having a wide range of applications starting from low power VLSI design, fault tolerant circuits, quantum computing to fields such as bio informatics. An ALU may be regarded as the processor's numerical calculator and logical operation evaluator. In this paper a fault tolerant reversible ALU design is proposed. Parity preserving logic gates are the main component in this design. A parity preserving gate is the one in which the parity of the input and the output vectors is the same. The proposed ALU can produce up to 16 logical and 16 arithmetic operations.

Parity preserving logic based fault tolerant reversible ALU

A Gray Code is an encoding of integers as sequences of bits with the property that the representations of adjacent integers differ in exactly one binary position. Gray Codes have many practical applications that go beyond research interests. There are different types of gray codes: Binary reflected, Maximum Gap, Balanced, Antipodal and Non Composite to name a few. On the other hand Reversible logic has received great attention due to their ability to reduce the power dissipation--an important aspect of low power circuit design. Other applications include Optical information processing, DNA computing, bio informatics, quantum computation and nanotechnology. Counters have a primary function of producing a specified output sequence and are thus sometimes referred to as pattern generators. This paper proposes design of different gray code counters using reversible logic gates, to draw comparative conclusions upon their performance.

T. R. Rakshith

Papers

Design of high speed low power multiplier using Reversible logic: A Vedic mathematical approach

Novel Code Converter Employing Reversible Logic

Optimized reversible vedic multipliers for high speed low power operations

Parity preserving logic based fault tolerant reversible ALU

Contemplation of synchronous Gray Code counter and its variants using reversible logic gates