Proceedings ArticleDOI
Design of high speed low power multiplier using Reversible logic: A Vedic mathematical approach
T. R. Rakshith,Rakshith Saligram +1 more
- pp 775-781
TLDR
A Vedic multiplier known as “Urdhva Tiryakbhayam” meaning vertical and crosswise, implemented using reversible logic, which is the first of its kind is brought out.Abstract:
Multipliers are vital components of any processor or computing machine. More often than not, performance of microcontrollers and Digital signal processors are evaluated on the basis of number of multiplications performed in unit time. Hence better multiplier architectures are bound to increase the efficiency of the system. Vedic multiplier is one such promising solution. Its simple architecture coupled with increased speed forms an unparalleled combination for serving any complex multiplication computations. Tagged with these highlights, implementing this with reversible logic further reduces power dissipation. Power dissipation is another important constraint in an embedded system which cannot be neglected. In this paper we bring out a Vedic multiplier known as “Urdhva Tiryakbhayam” meaning vertical and crosswise, implemented using reversible logic, which is the first of its kind. This multiplier may find applications in Fast Fourier Transforms (FFTs), and other applications of DSP like imaging, software defined radios, wireless communications.read more
Citations
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Proceedings ArticleDOI
Optimized reversible vedic multipliers for high speed low power operations
Rakshith Saligram,T. R. Rakshith +1 more
TL;DR: This paper aims to enhance the performance of the previous design of the reversible Urdhva Tiryakbhayam Vedic multiplier by using the Total Reversible Logic Implementation Cost (TRLIC) as an aid to evaluate the proposed design.
Proceedings ArticleDOI
Design and implementation of a high speed digital FIR filter using unfolding
TL;DR: The proposed design and implementation of a high speed digital Finite Impulse Response (FIR) filter is unfolded by a factor 3 which results in scheduling the filter to a smaller iteration period and along with this throughput of the filter also increases.
Journal ArticleDOI
Performance improvement of elliptic curve cryptography system using low power, high speed 16 × 16 Vedic multiplier based on reversible logic
S. Karthikeyan,M. Jagadeeswari +1 more
TL;DR: A high-speed 16 × 16 Vedic multiplier was designed using Urdhva Tiryagbhyam (UT) sutra, which is derived from Vedic mathematics, and a new method based on Elliptic Curve Cryptography (ECC) system for encryption and decryption using Vedic multiplication is proposed.
Proceedings ArticleDOI
Implementation of optimized high performance 4×4 multiplier using ancient Vedic sutra in 45 nm technology
TL;DR: To design a multiplier circuit based on Vedic sutras, the design of 2×2, 4×4 has been designed in DSCH2 and all the outputs have been given and the noise, power have been calculated by T-Spice-13 in 45nm Technology.
Proceedings ArticleDOI
Applications of vedic multiplier designs - A review
Akanksha Kant,Shobha Sharma +1 more
TL;DR: The objective of this paper is to encapsulate an array of applications of Vedic Multiplier in the vast domain of Image processing and Digital signal processing, particularly the different modifications of existing VedicMultiplier architectures enhancing their speed and performance parameters.
References
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