In this paper a review of the more "fundamental" concerns regarding the scaling of the gate dielectric in the ultrathin regime is presented. Material issues are discussed pertaining to the integration of silicon oxynitride and oxide/nitride stacked layers and how such films might reduce or minimize boron penetration problems and address leakage current and reliability concerns. A methodology is presented to calculate device and chip lifetimes for MOS structures on the basis of data extracted from voltage- and temperature-accelerated measurements. Some integration issues regarding higher-k materials are also discussed because of their ability to solve the scaling problem. However, difficulties are involved in integrating them into a CMOS process flow.

Scaling the gate dielectric: materials, integration, and reliability

This paper reviews recent progress in understanding microstructural and growth-mechanistic aspects of ultrathin (<4 nm) oxynitride films for gate dielectric applications. Different techniques for characterizing these films are summarized. We discuss several nitridation methods, including thermal (oxy)nitridation in NO, N2O, and N2 as well as a variety of deposition methods. We show that a basic understanding of the gas-phase and thin-film oxygen and nitrogen incorporation chemistries facilitates the processing of layered oxynitride nanostructures with desirable electrical properties.

Growth and characterization of ultrathin nitrided silicon oxide films

Extremely thin (equivalent oxide thickness, Teq=1.2 nm) silicon-nitride high-k (er=7.2) gate dielectrics have been formed at low temperatures (⩽550 °C) by an atomic-layer-deposition (ALD) technique with subsequent NH3 annealing at 550 °C. A remarkable reduction in leakage current, especially in the low dielectric voltage region, which will be the operating voltage for future technologies, has made it a highly potential gate dielectric for future ultralarge-scale integrated devices. Suppressed soft breakdown events are observed in ramped voltage stressing. This suppression is thought to be due to a strengthened structure of Si–N bonds and the smoothness and uniformity at the poly-Si/ALD-silicon-nitride interface.

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NH3-annealed atomic-layer-deposited silicon nitride as a high-k gate dielectric with high reliability

The thermal oxynitridation of Si(100) in nitric oxide (NO) has been studied by high resolution medium energy ion scattering for ultrathin films. The nitrogen depth distribution and the composition of the films have been accurately determined. It is observed that for NO-grown films the nitrogen is distributed relatively evenly in the film, unlike the sharply peaked distribution observed in the case of SiO2 films that were subsequently annealed in NO. The width of the nitrogen distribution, as well as the oxynitride thickness, increase with temperature. It is further found that the total amount of nitrogen in the film and the ratio of nitrogen to oxygen increases with increasing oxynitridation temperature. These results have significant impact on our understanding of how nitrogen can be positioned in next-generation gate dielectrics.

The composition of ultrathin silicon oxynitrides thermally grown in nitric oxide

A low thermal budget approach to monolayer-level controlled incorporation of nitrogen in ultrathin gate dielectrics using 300 °C, remote plasma processing is discussed. Incorporation of approximately 1 ML of nitrogen at the Si–SiO2 interface in an “N–O” structure has been achieved by remote plasma-assisted oxidation of the Si surface followed by N2/He remote plasma nitridation, each at a process pressure of 0.3 Torr. The interface nitridation reduces direct and Fowler–Nordheim tunneling by at least one order of magnitude, independent of film thickness. Incorporation of nitrogen at the top surface of the oxide in a concentration equivalent to about 1–2 molecular layers of silicon nitride in an “O–N” structure has been accomplished by N2/He remote plasma nitridation at 300 °C, but at a reduced process pressure of 0.1 Torr. Top surface nitridation has been shown to prevent boron diffusion out of p+ poly-Si gate electrodes during high-temperature activation anneals, e.g., at 1000 °C. Combining interfacial and...

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Monolayer-level controlled incorporation of nitrogen in ultrathin gate dielectrics using remote plasma processing: Formation of stacked “N–O–N” gate dielectrics

In this letter, we report on the impact of the suppression of boron diffusion via nitridation of SiO2 on gate oxide integrity and device reliability SiO2 subjected to rapid thermal nitridation in pure nitric oxide (NO) is used to fabricate thin oxynitride gate dielectrics Both n+ polycrystalline silicon (polysilicon) gated n‐MOS (metal–oxide semiconductor) and p+‐polysilicon gated p‐MOS devices were subjected to anneals of different times to study the effect of dopant diffusion on gate oxide integrity As expected, an advanced oxynitride gate dielectric will effectively alleviate the boron‐penetration‐induced flatband voltage instability in p+‐polysilicon gated p‐MOS capacitors due to the superior diffusion barrier properties However, such improvements are observed in conjunction with some degradation of the oxide reliability due to the boron‐blocking/accumulation inside the gate dielectric Results show that even though the oxide quality is slightly degraded for NO‐nitrided SiO2 with p+‐polysilicon ga

Degradation of oxynitride gate dielectric reliability due to boron diffusion

Ultrathin NO-nitrided SiO/sub 2/ has been demonstrated to be a promising gate dielectric for dual-gate CMOS to alleviate the boron penetration problem in BF/sub 2/-implanted polysilicon gated p-MOSFETs. Results indicate that for both n/sup +/-poly n-MOSFETs and p/sup +/-poly p-MOSFETs, devices with NO-nitrided SiO/sub 2/ gate dielectrics exhibit superior electrical characteristics as well as device reliability as compared to those with control SiO/sub 2/.

T.S. Chen

Papers

Degradation of oxynitride gate dielectric reliability due to boron diffusion

Suppressed boron penetration in P/sup +/-poly PMOSFETs with NO-nitrided SiO/sub 2/ gate dielectrics