Y
Yusuke Yamada
Researcher at Tohoku University
Publications - 15
Citations - 855
Yusuke Yamada is an academic researcher from Tohoku University. The author has contributed to research in topics: Wafer & Wafer bonding. The author has an hindex of 8, co-authored 15 publications receiving 830 citations.
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Journal ArticleDOI
Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections
Mitsumasa Koyanagi,T. Nakamura,Yusuke Yamada,H. Kikuchi,Takafumi Fukushima,Tetsu Tanaka,Hiroyuki Kurino +6 more
TL;DR: In this article, a 3D shared-memory test chip with three-stacked layers was fabricated by bonding the wafers with vertical buried interconnections after thinning.
Proceedings ArticleDOI
Three-dimensional shared memory fabricated using wafer stacking technology
K. W. Lee,T. Nakamura,Teruo Ono,Yusuke Yamada,T. Mizukusa,H. Hashimoto,Ki-Tae Park,Hiroyuki Kurino,Mitsumasa Koyanagi +8 more
TL;DR: It was demonstrated that the basic memory operation and the broadcast operation of 3D shared memory are successfully performed.
Proceedings ArticleDOI
New three-dimensional integration technology using self-assembly technique
TL;DR: In this article, a 3D SRAM test chip with ten memory layers was successfully fabricated using the super-smart-stack (SSS) technology using a self-assembly technique.
Proceedings ArticleDOI
New Three-Dimensional Integration Technology Based on Reconfigured Wafer-on-Wafer Bonding Technique
Takafumi Fukushima,H. Kikuchi,Yusuke Yamada,T. Konno,Jun Liang,K. Sasaki,K. Inamura,Tetsu Tanaka,Mitsumasa Koyanagi +8 more
TL;DR: Wang et al. as mentioned in this paper proposed a reconfigurable wafer-on-wafer bonding technique to solve several problems in 3D integration technology using the conventional wafer on wafer bonding techniques, which can obtain a high production yield even after bonding many wafers.
Journal ArticleDOI
New Three-Dimensional Integration Technology Using Chip-to-Wafer Bonding to Achieve Ultimate Super-Chip Integration
TL;DR: In this article, the authors investigated several key technologies of vertical interconnection formation, chip alignment, chip-to-wafer bonding, adhesive injection, and chip thinning to vertically stack known good dies (KGDs) into 3D LSI chips.