To overcome various concerns caused by scaling-down the device size, it is indispensable to introduce a new concept of heterogeneous 3D integration called a super-chip in which various kinds of device chips with different size, different devices and different materials are stacked. A key technology of self-assembly and electrostatic (SAE) temporary bonding has been developed to achieve a super-chip. Several kinds of super-chips are fabricated by stacking compound semiconductor device chip, photonic device chip and spintronic device chip on CMOS device chips.

Heterogeneous 3D integration — Technology enabler toward future super-chip

The impacts of Cu contamination from a backside surface of a thinned wafer and Cu via on device reliabilities in 3-D IC integration are electrically evaluated. Intrinsic gettering (IG) layer, which was formed by high density oxygen precipitate, shows excellent Cu retardation characteristics from the backside surface of the thinned wafer. Extrinsic gettering (EG) layer, which was formed by postgrinded dry polish (DP) treatment shows good Cu retardation characteristics compared with other postgrinded treatments. The minimal 30-nm-thick Ta barrier layer in Cu via shows good barrier property to Cu diffusion from Cu via after annealing up to 60 min at 300 °C. However, it is not enough at 400 °C annealing, because the generation lifetime shows significant degradation after the initial annealing for 5 min. The DRAM cell characteristics show severe shortening retention time after an intentional Cu diffusion from the backside of the thinned DRAM chip at relatively low temperature of 300 °C.

Impacts of Cu Contamination on Device Reliabilities in 3-D IC Integration

We developed silicon epitaxial wafers with high gettering capability by using hydrocarbon-molecular-ion implantation. These wafers also have the effect of hydrogen passivation on process-induced defects and a barrier to out-diffusion of oxygen of the Czochralski silicon (CZ) substrate bulk during Complementary metal-oxide-semiconductor (CMOS) device fabrication processes. We evaluated the electrical device performance of CMOS image sensor fabricated on this type of wafer by using dark current spectroscopy. We found fewer white spot defects compared with those of intrinsic gettering (IG) silicon wafers. We believe that these hydrocarbon-molecular-ion-implanted silicon epitaxial wafers will improve the device performance of CMOS image sensors.

Proximity Gettering Design of Hydrocarbon⁻Molecular⁻Ion⁻Implanted Silicon Wafers Using Dark Current Spectroscopy for CMOS Image Sensors.

https://www.jstage.jst.go.jp/article/elex/12/7/12_12.20152001/_pdf

Recent progress in 3D integration technology

The impacts of 3-D integration processes on memory retention characteristics in thinned DRAM chip were evaluated. The retention characteristics of DRAM cell in a DRAM chip which was face-down bonded to an interposer with under-fill degraded depending on the decreased chip thickness, especially dramatically degraded below 40- μm thickness. Meanwhile, the retention characteristics of DRAM cell in a DRAM chip which was bonded without under-fill relatively not so degraded until to 30- μm thickness, but suddenly degraded below 20- μm thickness. The retention characteristics of DRAM cell in the thinned DRAM chip which was CMP-treated dramatically degraded after intentional Cu diffusion from the backside surface at 300 °C annealing, regardless of the well structure. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip which was DP-treated not degraded even after Cu diffusion at 300 °C annealing.

Impacts of 3-D Integration Processes on Memory Retention Characteristics in Thinned DRAM Chip for High-Reliable 3-D DRAM

The influence of Cu diffusion at the backside surface of a thinned dynamic random access memory (DRAM) chip for 3-D integration on memory retention characteristics was electrically evaluated. A DRAM test chip was bonded to a Si interposer at 300 °C for 2 min and thinned down to 30-μm thickness. The DRAM cell characteristics, which show 50% failure at 200 μs, were not degraded from the packaged sample (prethinning) even after chip bonding, chip thinning, and no-Cu postannealing for 30 min at 300 °C. Meanwhile, the DRAM cell array shows 50% failure at 70 μs after an intentional Cu diffusion from the backside surface for 30 min at 300 ° C. It means that Cu atoms at the back surface reach the Si-SiO2 interface of the front surface in active areas and cause functional failures such as increasing carrier recombination rate, consequently shortening retention time. However, the NMOS transistor characteristics show no significant change even after Cu diffusion. The on-current performance characterized by majority carriers is not an effective criterion to characterize sensitively the Cu contamination effect.

Impact of Cu Contamination on Memory Retention Characteristics in Thinned DRAM Chip for 3-D Integration

Development of Biosignal Recording Board System with Agile Control of Circuit Characteristics for Various Biosignals

To enable chronic and stable neural recording, we have been developing an implantable multichannel neural recording system with impedance analysis functions. One of the important things for high-quality neural signal recording is to maintain well interfaces between recording electrodes and tissues. We have proposed an impedance analysis circuit with a very small circuit area, which is implemented in a multichannel neural recording and stimulating system. In this paper, we focused on the design of an impedance analysis circuit configuration and the evaluation of a minimal voltage measurement unit. The proposed circuit has a very small circuit area of 0.23 mm2 designed with 0.18 µm CMOS technology and can measure interface impedances between recording electrodes and tissues in ultrawide ranges from 100 Ω to 10 MΩ. In addition, we also successfully acquired interface impedances using the proposed circuit in agarose gel experiments.

https://iopscience.iop.org/article/10.7567/JJAP.55.04EM12/pdf

Design and evaluation of area-efficient and wide-range impedance analysis circuit for multichannel high-quality brain signal recording system

To enable chronic and stable neural recording, we introduce an implantable multichannel neural recording system with impedance analysis function. An important thing for high quality neural signal recording is how well recording electrodes are interfaced to tissue. We have proposed an impedance analysis circuit with very small circuit area which is implemented in multichannel neural recording and stimulating system. In this paper, we focus on the design of analysis circuit configuration and voltage measurement circuit. The proposed circuit has a very small circuit area of 0.23 mm 2 designed with 0.18-μm CMOS technology, and measures interface impedance with ultra wide range from 10 kΩ to 10 MΩ. In addition, we were also successful in acquiring impedances using agarose gel experiments.

Takaharu Tani

Papers

Impact of Cu Contamination on Memory Retention Characteristics in Thinned DRAM Chip for 3-D Integration

Development of Biosignal Recording Board System with Agile Control of Circuit Characteristics for Various Biosignals

Design and evaluation of area-efficient and wide-range impedance analysis circuit for multichannel high-quality brain signal recording system

Area-Efficient and Wide-Range Impedance Analysis Circuit for Multichannel High Quality Brain Signal Recording System

Development of Biosignal Recording Board System with Agile Control of Circuit Characteristics for Various Biosignals