Showing papers by "Timo Hämäläinen published in 2001"
07 May 2001
TL;DR: Three implementations of triple data encryption standard (3DES) algorithm on a configurable platform with small area and reasonable throughput are presented and the set requirements are met and the cipher can be integrated into the system.
Abstract: This paper presents three implementations of triple data encryption standard (3DES) algorithm on a configurable platform. Implementations are aimed at the medium access control (MAC) protocol of a multimedia-capable wireless local area network (WLAN). For this reason, very strict timing constraints as well as demands for area-efficiency are present. The MAC processing is handled by a digital signal processor (DSP) and a Xilinx Virtex field programmable gate array (FPGA) chip. The latter one is also used for the presented encryption implementations. As a result of the study, 3DES implementations with small area and reasonable throughput and, on the contrary, with large area and very high throughput are realized. Even though 3DES turns out to be quite large and resource-demanding, the implementations still leave enough chip area for the other MAC functions. Consequently, the set requirements are met and the cipher can be integrated into the system.
30 citations
01 Jan 2001
TL;DR: A study of the kind of performance trade-offs that can be made by changing the description style ininite state machine optimisation, and shows at least two times better performance of speed or area in the best description compared with the worst.
Abstract: Finite state machine (FSM) optimisation has usually been studied through state assignment, state vector encoding, and combinational logic optimisation. Such details should not be consequential in behavioural descriptions. On the other hand, describing correct and efficient hardware structures in VHDL (VHSIC hardware description language), or generally in any high-level description language, is more a question of description style than correct language statements. Therefore, more or less conscious choices are made in the design description itself that guide the synthesis software toward a specific implementation. The best implementation is also dependent on the target technology and, therefore, there is no single best description style for all FSMs. The paper is a study of the kind of performance trade-offs that can be made by changing the description style. A program is shown to be able to generate these different descriptions from an intermediate format (kiss2) describing the FSM. Therefore, this process for finding a better description could be automated and performed by the synthesis software itself. Descriptions are tested on a set of 13 FSMs most from a benchmark suite LGSynth93. The results show at least two times better performance of speed or area in the best description compared with the worst. In performance critical applications this difference can be of a crucial importance.
29 citations
07 May 2001
TL;DR: A new video encoder proposal, H.26L, is compared against H.263 and H.264 and the trade-off possibilities between the complexity and compression performance within H.262 are presented.
Abstract: A new video encoder proposal, H.26L, is compared against H.263 and H.263+. In the comparison, both computational complexity and compression performance are analyzed. Moreover, the trade-off possibilities between the complexity and compression performance within H.26L are presented. Experimental comparisons with H.263 and H.263+ show that H.26L reduces the output bit rate about 30% with the same quality. The computation time increases about three times compared to H.263 and leads into the encoding speed of 3-6 fps for QCIF sequences on a 400 MHz Pentium III processor. Realtime operation can be achieved by applying additional, algorithmic and platform-specific optimizations.
29 citations
Patent•
28 Sep 2001
TL;DR: In this article, the authors present a method and arrangements for handling, within a communications system comprising a distributed domain (301) and a central domain (303), electronic records that contain predictions of the outcome of a certain incident.
Abstract: Methods and arrangements are provided for handling, within a communications system comprising a distributed domain (301) and a central domain (303), electronic records that contain predictions of the outcome of a certain incident. Within the distributed domain (301) there is generated (304), before the outcome of the incident is known, a multitude of electronic records that contain predictions of the outcome of the incident. The electronic records are conveyed (305) from the distributed domain (301) to the central domain (303). After the outcome of the incident is known, the central domain (303) finds out (306) which of the electronic records, if any, contain correct predictions of the outcome of the incident. Each of the electronic records is furnished (304, 401, 502, 902, 1202, 1911), within the distributed domain (301), with a cryptographically protected proof of a certain moment of time associated with the generation of the electronic record. The central domain (303) accepts (306, 1430, 2011) only those of the electronic records conveyed thereto as valid for which the cryptographically protected proof of a certain moment of time associated with the generation of the electronic record shows that said certain moment of time was not later in time than a certain time limit.
25 citations
25 Nov 2001
TL;DR: This paper presents a new methodology based on economic models to provide Quality of Service (QoS) guarantees to competing traffic classes (classes of sessions) in packet networks.
Abstract: This paper presents a new methodology based on economic models to provide Quality of Service (QoS) guarantees to competing traffic classes (classes of sessions) in packet networks. We consider an economic model of a packet network where resources are priced. As the demand for network services accelerates, users' satisfaction to the service level might decrease due to congestion at the network nodes. To prevent this, efficient allocation of network resources, such as available bandwidth and switch capacity, is needed. By using so-called user profile as well as utility (e.g. data rate) functions, it is possible to allocate data rates and other utilities using arbitrary number of QoS classes, say 0.01,..., 10. Maximal capacity of the data network infrastructure is exploited by using a dynamic allocation strategy.
18 citations
26 Sep 2001
TL;DR: Two optimized implementations of the emerging ITU-T H.26L video encoder are described, the first, medium-optimized version, is implemented in C and the latter, highly optimized version, utilizes MMX assembly instructions.
Abstract: Two optimized implementations of the emerging ITU-T H.26L video encoder are described. The first, medium-optimized version, is implemented in C and the latter, highly optimized version, utilizes MMX assembly instructions. Comparisons to a correspondingly optimized H.263/H.263+ implementation are given with the spatial and temporal video quality fixed and the bit rate and complexity varied. On a 733 Pentium III processor, a real-time encoding speed of 10 fps for QCIF (quarter common intermediate format) sequences is achieved with a 29% reduction in bit rate compared to H.263+. The complexity of H.26L is about 3.4 times more than that of H.263+.
16 citations
19 Jun 2001
TL;DR: An optimized implementation of an H.26L video encoder is presented, which reduces the output bit rate about 25% at the expense of increased complexity but enables real-time operation on a 733 MHz general-purpose processor.
Abstract: An optimized implementation of an H.26L video encoder is presented. Compared to H263, H.26L reduces the output bit rate about 25% at the expense of increased (3.8X) complexity. However, optimizations enable real-time operation on a 733 MHz general-purpose processor.
16 citations
01 Jan 2001
TL;DR: A passenger information system (PIS) called TUTPIS has been developed for networking passengers with companies that provide public transport services and the behaviour of external entities, such as buses, trains, and third party systems is implemented for simulations.
Abstract: A passenger information system (PIS) called TUTPIS has been developed for networking passengers with companies that provide public transport services. TUTPIS supports a passenger with personalised, real time information services in all phases of a journey. Services include timetables, travel route searching, route reservations, and electronic payment. TUTPIS is targeted to operate on the developing wireless network infrastructure of mobile, local, and personal networking technologies. A TUTPIS model concentrating on bus services has been implemented using the specification and description language (SDL). The model contains functional implementations of a TUTPIS server and mobile terminals. In addition, the behaviour of external entities, such as buses, trains, and third party systems is implemented for simulations. By simulations, the operability of TUTPIS can be verified and performance estimations for system servers, wireless network throughputs, and mobile terminals derived.
13 citations
29 Oct 2001
TL;DR: A two-level distributed Web architecture is presented that uses a QoS-aware load-balancing algorithm to significantly reduce the mean response times by taking into account both stale load information and content-based scheduling when choosing a server for a incoming request for globally distributed Web systems.
Abstract: The use of Web servers is growing tremendously, but their performance and reliability haven't been improved at the same rate. Users of highly popular Web sites may experience long. delays when accessing information. In this paper, we present a two-level distributed Web architecture that uses our QoS-aware load-balancing algorithm to significantly reduce the mean response times by taking into account both stale load information and content-based scheduling when choosing a server for an incoming request for globally distributed web systems. To achieve better end-to-end Quality of Service (QoS), different Classes of Service (CoS) of the customers are considered as one parameter in the load-balancing algorithm.
7 citations
06 May 2001
TL;DR: It is shown that TTAs are at least equal to commercial processors in performance and the performance level is achieved at far lower cost.
Abstract: The paper studies a configurable processor architecture, transport triggered architecture (TTA), for encryption algorithm implementations. The automatic TTA design space exploration is applied and configurations with good cost-performance ratio are found. It is shown that TTAs are at least equal to commercial processors in performance. According to earlier studies the performance level is also achieved at far lower cost. This encourages further development with tuned functionality.
7 citations
09 Jul 2001
TL;DR: A content based scheduling algorithm which can be used at the front-end of the server cluster is presented which uses the content information of the requests and the load on the back servers to choose the server to handle each request.
Abstract: This paper introduces a novel algorithm for content based switching. A content based scheduling algorithm (QoS Aware Load Balancing Algorithm, QoS-LB) which can be used at the front-end of the server cluster is presented. The front-end switch uses the content information of the requests and the load on the back servers to choose the server to handle each request. At the same time, different Quality of Service (QoS) classes of the customers can be considered as one parameter in the load balancing algorithm. This novel feature becomes more important when service providers begin to offer the same services for customers with different priorities.
Book•
01 Jun 2001TL;DR: This chapter focuses on parallel implementations of the Self-Organizing Map (SOM) featuring different levels of parallelism, considered in great detail as it is the most commonly used approach.
Abstract: This chapter focuses on parallel implementations of the Self-Organizing Map (SOM) featuring different levels of parallelism. The basic arithmetic-logical operations of SOM are first reviewed for a consideration of implementation issues such as number precision, memory consumption and time complexity. Mapping involves network, training set, neuron and weight parallelism. Examples of the weight and neuron parallel mappings are given for abstract platforms to conduct general principles. Neuron parallel mapping is considered in great detail as it is the most commonly used approach. A review of implementations is given from supercomputers to VLSI (Very Large Scale Integration) chips with criteria for performance comparison.
06 May 2001
TL;DR: A parallel implementation of H.263/MPEG-4 video encoder for Common Intermediate Format (CIF, 352/spl times/288) pictures is presented and experimental results show real-time encoding speed of 30 fps has been reached using configuration of a master and two slave encoding DSPs.
Abstract: A parallel implementation of H.263/MPEG-4 video encoder for Common Intermediate Format (CIF, 352/spl times/288) pictures is presented. The implementation runs on Hunt Engineering's Hepc/spl delta/ DSP-carrier featuring four TMS320C6201 ICs. The experimental results show real-time encoding speed of 30 fps has been reached using configuration of a master and two slave encoding DSPs. In addition, DSP-to-DSP link requirements, image quality vs. bit rate, scalability and frame rate performance are measured and analyzed.
06 May 2001
TL;DR: Interfacing RISC and DSP processors as Intellectual Property blocks for an MPEG-4 baseline video encoder is presented, using Heterogeneous IP Block Interconnection as a base for contemporary System-on-Chip implementations.
Abstract: Interfacing RISC and DSP processors as Intellectual Property blocks for an MPEG-4 baseline video encoder is presented. Our previously presented Heterogeneous IP Block Interconnection (HIBI) architecture is used as a base for contemporary System-on-Chip implementations. Cost effective, general-purpose processor cores and DSPs lacking a native HIBI support need very low-delay interfacing units that are explained in detail in this paper. Interfaces are written in synthesisable VHDL and verified in Mentor Seamless CVE co-verification environment.
25 Nov 2001
TL;DR: This work focuses on the development of a high-performance, cache-based architecture that is general enough to support most type of server applications and should enable the server to achieve very close to the maximum performance that the architecture can achieve.
Abstract: The low cost and variety of future clients (e.g., PDAs, laptops, pagers, printers, and specialized appliances) will result in a larger number of client devices per user. Thin clients will have fast processors, but little or no disk storage so that they will download most of their data and executables. The existence of cheap client hardware with high-resolution graphics and high-quality audio together with high-bandwidth networks will probably lead to applications with increasing demands on network and server performance. We focus on the development of a high-performance, cache-based architecture that is general enough to support most type of server applications. Such an architecture should enable the server to achieve very close to the maximum performance that the architecture can achieve. In addition, customizability and handling heterogeneous objects are also relevant to the architecture because it must be general enough to support a wide variety of applications with different QoS needs.
TL;DR: The roles of the different providers that will interact with each other and new service types that will be developed and exploited with the new technology and the ways to charge services in 3G world in an appropriate manner for customers and operators are presented.
Abstract: The 3G/UMTS-networks and services will provide a wide range of telecommunication services. To achieve, this, we need a new view to networks, network services and service abilities. The amount of service providers in the 3G networks will be at least the same than in the present Internet. The amount of users in the 3G networks will overgrow the user amount of Internet forming a global worldwide communication society. This paper discusses customer billing in the 3G world. There are some main issues that are not very, clear to all 3G service and network providers, which however, should be settled before, 3G networks are operational. One of the most important matters is the QoS (Quality of Service), which is needed to achieve all benefits of the 3G networks. Here, we present the roles of the different providers that will interact with each other. New service types that will be developed and exploited with the new technology and the ways to charge services in 3G world in an appropriate manner for customers and operators is also presented. Not all of the details will be discussed here, but the main issues are covered and the one goal is to start discussions of this important issue among customers and service providers.
29 Oct 2001
TL;DR: A model that can be used to share network capacity among customers under different traffic conditions, suitable for multiservice networks, such as the Internet, to support connections of given duration that require a certain quality of service is introduced.
Abstract: This paper introduces a model that can be used to share network capacity among customers under different traffic conditions. This model is suitable for multiservice networks, such as the Internet, to support connections of given duration that require a certain quality of service. We study different types of network traffic mixed in the same telecommunication link. A single link is considered as a bottleneck and the goal is to find the customer profile that maximizes the revenue of the operator.
29 Oct 2001
TL;DR: This paper presents a generic simulation model, which can be used to develop and study caching algorithms, and utilizes this model in developing new cache-maintaining methods, which support CoS, scale to multiple server farms, and are optimized to achieving high throughput.
Abstract: The WWW employs a hierarchical data dissemination architecture in which hypermedia objects stored at a remote server are delivered to clients across the Internet and cached on disks at intermediate proxy servers. One of the objectives of Web caching algorithms is to maximize the amount of data transferred through the proxy servers or cache hierarchies. In this paper, we present a generic simulation model, which can be used to develop and study caching algorithms. Our goal is to utilize this model in developing new cache-maintaining methods, which support CoS, scale to multiple server farms, and are optimized to achieving high throughput.
29 Oct 2001
TL;DR: An algorithm for the network link allocation is introduced that allocates resources between two network devices and the maximal capacity of the data network infrastructure is exploited.
Abstract: We introduce an algorithm for the network link allocation. The link may be wired or wireless, so this method can be adapted e.g. in 3G networks. The algorithm allocates resources between two network devices. It is possible to allocate data rates using arbitrary number of user QoS classes, say $ 0.1, $ 0.2,..., $ 10. The maximal capacity of the data network infrastructure is exploited. The performance of the algorithm is justified from the maximum likelihood point of view.