An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A light-emitting device package including: a package main body including a cavity and a lead frame including a mounting portion disposed in the cavity and a plurality of terminal portions; a light-emitting device chip mounted on the mounting portion; a plurality of bonding wires for electrically connecting the plurality of terminal portions and the light-emitting device chip; a light-transmitting encapsulation layer filled in the cavity; and a light-transmitting cap member disposed in the cavity and blocking the encapsulation layer to contact the plurality of bonding wires.

Light emitting device package

An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

Methods of forming metal-doped chalcogenide layers and devices containing such doped chalcogenide layers include using a plasma to induce diffusion of metal into a chalcogenide layer concurrently with metal deposition. The plasma contains at least one noble gas of low atomic weight, such as neon or helium. The plasma has a sputter yield sufficient to sputter a metal target and a UV component of its emitted spectrum sufficient to induce diffusion of the sputtered metal into the chalcogenide layer. Using such methods, a conductive layer can be formed on the doped chalcogenide layer in situ. In integrated circuit devices, such as non-volatile chalcogenide memory devices, doping of the chalcogenide layer concurrently with metal deposition and formation of a conductive layer in situ with the doping of the chalcogenide layer reduces contamination concerns and physical damage resulting from moving the device substrate from tool to tool, thus facilitating improved device reliability.

Integrated circuit device and fabrication using metal-doped chalcogenide materials

We present the development of a polyimide-based two-dimensional tactile sensing array realized using a novel inverted fabrication technique. Thermal silicon oxide or Pyrex® substrates are treated such that their surfaces are OH group terminated, allowing good adhesion between such substrates and a spun-on polyimide film during processing through what are suspected to be hydrogen bonds that can be selectively broken when release is desired. The release of the continuous polyimide film is rapidly accomplished by breaking these bonds. This process results in robust, low-cost and continuous polymer-film devices. The developed sensor skin contains an array of membrane-based tactile sensors (taxels). Micromachined thin-film metal strain gauges are positioned on the edges of polyimide membranes. The change in resistance from each strain gauge resulting from normal forces applied to tactile bumps on the top of the membranes is used to image force distribution. Response of an individual taxel is characterized. The effective gauge factor of the taxels is found to be approximately 1.3. Sensor array output is experimentally obtained. The demonstrated devices are robust enough for direct contact with humans, everyday objects and contaminants without undue care.

https://iopscience.iop.org/article/10.1088/0960-1317/13/3/302/pdf

Development of polyimide flexible tactile sensor skin

A process of patterning a conductive layer on a substrate avoiding webbing yet permitting high density patterning places two layers between the resist and the metal. The first layer is an antireflective coating such as titanium nitride applied to the metal. The second layer is a barrier comprising silicon such as sputtered silicon or SiO₂. The barrier layer may also be a thin coating of spin-on glass. The barrier layer prevents interaction between the TiN and acid groups which are generated during exposure of the resist. With this structure in place the resist is applied, exposed and developed.

Bilayer metallization cap for photolithography

An opening in an insulator on a substrate is self-aligned to a reflective region on the substrate. The opening is formed by shining blanket radiation on photoresist on the insulator and developing to open the resist and insulator. The resist region that is above the reflective region absorbs both incident and reflected radiation, a larger total dose of radiation than is absorbed by resist above non-reflective regions. The incident dose is adjusted to provide a below threshold dose everywhere except to those regions of resist that are above highly reflective regions.

Self-aligned pattern over a reflective layer

A system and method for eliminating undercut when forming a C4 solder bump for BLM (Ball Limiting Metallurgy) and improving the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned by CMP with a bottom conductive layer of the barrier metal stack removed by etching. The diffusion barrier and C4 solder bump may be formed by electroless plating, in one embodiment, using a maskless technique, or by an electroplating techniques using a patterned mask. This allows the pitch of the C4 solder bumps to be reduced.

Undercut-free blm process for pb-free and pb-reduced c4

A structure and method of fabricating a semiconductor corrosion resistant metal fuse line including a refractory liner which can also act as a resistor is disclosed. Fabrication is accomplished using damascene process. The metal structure can be formed on a semiconductor substrate including a first portion including a first layer and a second layer, the first layer having higher resistivity than the second layer, the second layer having horizontal and vertical surfaces that are in contact with the first layer in the first portion, and a second portion coupled to the first portion, the second portion being comprised of the first layer, the first layer not being in contact with the horizontal and vertical surfaces of the second layer in the second portion. The metal structure can be used as a corrosion resistant fuse. The metal structure can also be used as a resistive element. The high voltage tolerant resistor structure allows for usage in mixed-voltage, and mixed signal and analog/digital applications. The resistor element has low capacitance, low skin effect, high linearity, a high melting temperature, and a high critical current to failure. The resistor structure can be formed on the walls of a dielectric trough. The structure can be applied to circuit applications such as an ESD network, an RC-coupled MOSFET, a resistor ballasted MOSFET and others. The resistors can be in series with the MOSFET or other structures.

Post-fuse blow corrosion prevention structure for copper fuses

An electrical interconnection structure. The electrical structure comprises a substrate comprising electrically conductive pads and a first dielectric layer over the substrate and the electrically conductive pads. The first dielectric layer comprises vias. A metallic layer is formed over the first dielectric layer and within the vias. A second dielectric layer is formed over the metallic layer. A ball limiting metallization layer is formed within the vias. A photoresist layer is formed over a surface of the ball limiting metallization layer. A first solder ball is formed within a first opening in the photoresist layer and a second solder ball is formed within a second opening in the photoresist layer.

Timothy H. Daubenspeck

Papers

Bilayer metallization cap for photolithography

Self-aligned pattern over a reflective layer

Undercut-free blm process for pb-free and pb-reduced c4

Post-fuse blow corrosion prevention structure for copper fuses

Electrical interconnection structure formation