[신간의 별자리x] 우리/미술, 그리고 ‘슬픔의 박물관’

ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESD in Integrated Circuits Effects of Processing and Packaging.

ESD in silicon integrated circuits

A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-/spl mu/m CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-/spl mu/m CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV.

Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Top layers of metal for high performance IC's

An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Integrated chip package structure using organic substrate and method of manufacturing the same

Biased and terminated p-n-p transistor chains are made from floating n-wells in p-substrate complementary metal-oxide semiconductor (CMOS) and used for power supply electrostatic discharge (ESD) clamps. The p-n-p gain may allow a compact termination circuit to be used, resulting in a stand-alone clamp. Bipolar p-n-p action accounts for unwanted low-voltage conduction as well as for very desirable clamping of power supply overvoltages. Bias networks are used to prevent excessive leakage at high temperature. These devices are becoming crucial to success in ESD product testing of CMOS integrated circuits.

Novel clamp circuits for IC power supply protection

Biased and terminated p-n-p transistor chains are made from floating n-wells in p-substrate CMOS and used for power supply ESD clamps. The p-n-p gain may allow a compact termination circuit to be used, resulting in a stand-alone clamp. Bipolar p-n-p action accounts for unwanted low-voltage conduction as well as for very desirable clamping of power supply overvoltages. Bias networks are used to prevent excessive leakage at high temperature. These devices are becoming crucial to success in ESD product testing of CMOS integrated circuits.

Using new techniques it is possible to construct an EOS/ESD equivalent circuit of a product. Location of energy dissipation during an EOS/ESD event is determined by a pulsed near infrared technique. Rules for predicting location of ESD dissipation are defined. N+-P-N+ structures and n-channel transistors suffer from a current lock-on effect, which is apparently caused by a runaway oxide trapping mechanism. Different failure mechanisms are observed at narrow and wide pulse widths. Hot electron induced damage occurs under mechanical handling conditions. On CMOS outputs the n-channel device absorbs most of the ESD, and is very fragile.

ESD on CHMOS Devices - Equivalent Circuits, Physical Models and Failure Mechanisms

Two ESD clamp circuit design techniques have been developed to reduce cell size and to combat the effects of gate leakage that have become significant in recent generations of digital CMOS process technology. Such clamps have proven to be able to withstand HBM stresses of 6kV and CDM pulses of 1.2kV.

http://ieeexplore.ieee.org/iel5/5238474/5266983/05267046.pdf

Timothy J. Maloney

Papers

Novel clamp circuits for IC power supply protection

Novel clamp circuits for IC power supply protection

ESD on CHMOS Devices - Equivalent Circuits, Physical Models and Failure Mechanisms

New considerations for MOSFET power clamps

Designing on-chip power supply coupling diodes for ESD protection and noise immunity☆