Open AccessProceedings Article
New considerations for MOSFET power clamps
Steven S. Poon,Timothy J. Maloney +1 more
- pp 1-5
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TLDR
Two ESD clamp circuit design techniques have been developed to reduce cell size and to combat the effects of gate leakage that have become significant in recent generations of digital CMOS process technology.Abstract:
Two ESD clamp circuit design techniques have been developed to reduce cell size and to combat the effects of gate leakage that have become significant in recent generations of digital CMOS process technology. Such clamps have proven to be able to withstand HBM stresses of 6kV and CDM pulses of 1.2kV.read more
Citations
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Boosted and distributed rail clamp networks for ESD protection in advanced CMOS technologies
TL;DR: A new, area efficient, boosted and distributed active MOSFET rail clamp network for I/O pad ESD protection is presented and a compact new rail clamp trigger circuit with high resistance to false triggering is introduced.
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A compact, timed-shutoff, MOSFET-based power clamp for on-chip ESD protection
TL;DR: In this paper, a RC-triggered, MOSFET-based power clamp for on-chip ESD protection is presented, which results in reduced capacitor area and reduced leakage at power-up.
Proceedings Article
Boosted and distributed rail clamp networks for ESD protection in advanced CMOS technologies
Michael Stockinger,James W. Miller,Michael G. Khazhinsky,C.A. Torres,James C. Weldon,B. D. Preble,Martin Bayer,Matthew D. Akers,V. G. Kamat +8 more
TL;DR: In this article, a new, area efficient, boosted and distributed active MOSFET rail clamp network for I/O pad ESD protection is presented, and a compact new rail clamp trigger circuit with high resistance to false triggering is introduced.
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ESD protection solutions for high voltage technologies
B. Keppens,Markus Paul Josef Mergens,Cong Son Trinh,Cornelius Christian Russ,B. Van Camp,K. Verhaege +5 more
TL;DR: In this article, different case studies are presented for ESD protection based on latch-up immune SCR devices, which is challenging due to narrow ESD design windows, NMOS degradation issues and the creation of unexpectedly weak parasitic devices.
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Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test
Ming-Dou Ker,Cheng-Cheng Yen +1 more
TL;DR: The proposed power-rail ESD clamp circuit can provide high enough chip- level ESD robustness, and without suffering the latchup-like failure during the system-level ESD test.
References
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Proceedings ArticleDOI
A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects
Sunit Tyagi,Mohsen Alavi,Robert M. Bigwood,T. Bramblett,J. Brandenburg,W. Chen,B. Crew,Makarem A. Hussein,P. Jacob,C. Kenyon,C. Lo,B. McIntyre,Z. Ma,Peter K. Moon,P. Nguyen,L. Rumaner,R. Schweinfurth,Swaminathan Sivakumar,M. Stettler,Scott E. Thompson,B. Tufts,J. Xu,Simon Yang,M. Bohr +23 more
TL;DR: In this paper, a leading edge 130 nm generation logic technology with 6 layers of dual damascene Cu interconnects is reported, where dual Vt transistors are employed with 1.5 nm thick gate oxide and operating at 1.3 V.
Journal ArticleDOI
Stacked PMOS clamps for high voltage power supply protection
Tim Maloney,Wilson Kan +1 more
TL;DR: High voltage designs are extensions of the large PMOS FET ESD clamps and timed drive circuitry that are used to clamp ordinary on-chip power supply lines.
Proceedings ArticleDOI
A modular 0.13 /spl mu/m bulk CMOS technology for high performance and low power applications
L.K. Han,S. Biesemans,John E. Heidenreich,K. Houlihan,Chuan Lin,Vincent J. McGahay,T. Schiml,A. Schmidt,Uwe Schroeder,M. Stetter,C. Wann,D. Warner,Reinhard Mahnkopf,Bomy A. Chen +13 more
TL;DR: A modular triple gate oxide process concept is introduced for the first time to allow the optimization of high performance devices, low leakage devices, and I/O devices independently to support deep-trench based embedded DRAM applications.
Journal ArticleDOI
Designing power supply clamps for electrostatic discharge protection of integrated circuits
TL;DR: In this article, power clamping can occur across comparable power supplies or between a power supply and ground; there are diode and field effect transistor (FET) methods for each.
Patent
Apparatus providing electrostatic discharge protection and method therefor
TL;DR: In this paper, an RC timer is used to control the operation of two or more tiers within the ESD circuit, and the RC timer can also be used for controlling the two-tier ESD circuits.