There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

This paper describes the ATLAS experiment as installed in i ts experimental cavern at point 1 at CERN. It also presents a brief overview of the expec ted performance of the detector.

http://absimage.aps.org/image/SES08/MWS_SES08-2008-020010.pdf

The ATLAS Experiment at the CERN Large Hadron Collider

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

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Electronic Transport In Mesoscopic Systems

我的台灣, 看見心靈的故鄉 =2009林磐聳藝術與設計展

We have investigated the electron mobility in ultrathin-body InGaAs-on-insulator devices using physics-based modeling that self-consistently accounts for quantum confinement and covers band-structure effects in ultrathin III-V layers. Scattering by nonpolar and polar acoustic and optical phonons, surface roughness, and thickness fluctuations, Coulomb and alloy disorder have been included in the calculations. The modeling, calibrated and verified on experimental data from the literature, has revealed a strong influence of thickness fluctuations caused by the light effective mass of Γ valley electrons. Our results indicate that InGaAs-on-insulator MOSFETs are more influenced by interface properties compared with silicon-on-insulator devices and outperform them only above certain body thickness that depends on interface quality.

Assessment of Electron Mobility in Ultrathin-Body InGaAs-on-Insulator MOSFETs Using Physics-Based Modeling

Front-gate and back-gate potential distributions and threshold voltage of recessed source/drain (ReS/D) ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are modeled. The analytical expressions of the front-gate and the back-gate potential distributions are derived by assuming a parabolic potential variation perpendicular to channel and by solving 2D Poisson’s equation. Based on strong inversion criterion applied to the surface potential minimum value, threshold voltage model of the short channel ReS/D UTB SOI MOSFETs is derived. The model is verified by comparison with 2D numerical device simulator over a wide range of different material and geometrical parameters and very good agreement is obtained.

Analytical models of front- and back-gate potential distribution and threshold voltage for recessed source/drain UTB SOI MOSFETs

Improving bulk FinFET DC performance in comparison to SOI FinFET

We present an extensive study of the electronic properties and carrier transport in phosphorene nanoribbons (PNRs) with edge defects by using rigorous atomistic quantum transport simulations. This study reports on the size- and defect-dependent scaling laws governing the transport gap, and the mean free path and carrier mobility in the PNRs of interest for future nanoelectronics applications. Our results indicate that PNRs with armchair edges (aPNRs) are more immune to defects than zig-zag PNRs (zPNRs), while both PNR types exhibit superior immunity to defects relative to graphene nanoribbons (GNRs). An investigation of the mean free path demonstrated that even in the case of a low defect density the transport in PNRs is diffusive, and the carrier mobility remains a meaningful transport parameter even in ultra-small PNRs. We found that the electron–hole mobility asymmetry (present in large-area phosphorene) is retained only in zPNRs for W > 4 nm, while in other cases the asymmetry is smoothed out by edge defect scattering. Furthermore, we showed that aPNRs outperform both zPNRs and GNRs in terms of carrier mobility, and that PNRs generally offer a superior mobility-bandgap trade-off, relative to GNRs and monolayer MoS2. This work identifies PNRs as a promising material for the extremely scaled transistor channels in future post-silicon electronic technology, and presents a persuasive argument for experimental work on nanostructured phosphorene.

Immunity of electronic and transport properties of phosphorene nanoribbons to edge defects

A new horizontal current bipolar transistor (HCBT) with a single polysilicon region and a CMOS gate polysilicon near the n+ emitter region is integrated with CMOS technology with the addition of two or three masks (three or four masking steps) and a small number of additional fabrication steps. The single-poly HCBT with an optimized collector exhibits fT and fmax of 51 and 61 GHz, respectively, and an fTBVCEO product of 173 GHz · V, which are the best reported HCBT characteristics to date and among the highest performance Si BJTs. An HCBT with only two additional masks to CMOS has fT and fmax of 43 and 53 GHz, respectively, and an fTSVCEO product of 120 GHz · V. The developed innovative fabrication techniques enable a very low-cost BiCMOS platform for wireless communication circuits.

Tomislav Suligoj

Papers

Assessment of Electron Mobility in Ultrathin-Body InGaAs-on-Insulator MOSFETs Using Physics-Based Modeling

Analytical models of front- and back-gate potential distribution and threshold voltage for recessed source/drain UTB SOI MOSFETs

Improving bulk FinFET DC performance in comparison to SOI FinFET

Immunity of electronic and transport properties of phosphorene nanoribbons to edge defects

Horizontal Current Bipolar Transistor With a Single Polysilicon Region for Improved High-Frequency Performance of BiCMOS ICs