This paper describes Cu direct bonding at room temperature for wearable micro-LED display. Still, the conventional bonding methods of micro-LEDs with solder micro-bumps have heat problems during bonding and difficulty achieving a narrow pitch. Using a unique method developed in this paper, it is possible to bond micro-LEDs to a 3D-IC chiplet without using the micro-bumps. Here, The 30 x 30 arrays of 0.1-mm-square blue micro-LEDs are assembled, bonded, and interconnected on a sapphire substrate through electroplated Cu, and successful emission from the blue micro-LEDs is confirmed. The bonding strength of the room-temperature Cu direct bonding with the micro-LEDs and a yield enhancement technique is also described. Finally, we emphasize the high potential of massively parallel chiplet self-assembly using liquid surface tension.

Room-Temperature Cu Direct Bonding Technology Enabling 3D Integration with Micro-LEDs

This letter describes a direct Cu bonding technology to there-dimensionally integrate heterogeneous dielets based on a chip-on-wafer configuration. 100- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> -cubed blue <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> LEDs temporarily adhered on a photosensitive resin are interconnected by semi-additive plating (SAP) without thermal compression bonding. By using SAP bonding, a lot of dielets can be stacked on thin 3D-IC chiplets. The following three key technologies are applied to solve the yield issues of SAP bonding. After pick-and-place assembly, additional coplanarity enhancement eliminates Cu bridges grown to a small gap between the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> LEDs and photosensitive resin. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> LEDs arrays with sidewalls insulated by room-temperature ozone-ethylene-radical (OER)-SiO2-CVD are successfully bonded on sapphire wafers and a thin 3D-IC with through-Si via (TSV). Further design optimization is required, but partial seed pre-etching works well to increase the yield. Fully integrated module implementation with the 3D-ICs will be the next stage, however, we discuss a superior prospect for yield enhancement toward nearly 100%. 

/pdf/room-temperature-direct-cu-semi-additive-plating-sap-bonding-2wgokuir.pdf

Room-Temperature Direct Cu Semi-Additive Plating (SAP) Bonding for Chip-on-Wafer 3D Heterogenous Integration With μLED

Fan-out panel-level packaging (FO-PLP) has become a critical forward-looking technology because it can meet the demands for small size, high input–output counts, and multichip functions. Moreover, a 3-D stacked architecture called packaging-on-packaging can be achieved using the interconnects of Cu pillars. The serious warpage issue of FO-PLP during the manufacturing process, however, causes many problems, such as assembly difficulty, low device reliability, and poor product yield. To address these problems, this study presents a process-oriented finite element analysis (FEA) method to estimate the variation of the whole warpage resulting from the mismatch among the coefficients of thermal expansion (CTEs) of dissimilar materials during the fabrication procedures. Notably, the model construction of the complex redistribution layer (RDL) in the proposed FO-PLP encounters a serious challenge when the simulated estimation is performed. Consequently, an equivalent mechanical characteristic extracted through simulation is adopted to redefine the material properties of RDL and Cu pillars separately. Moreover, the modified Timoshenko bi-layered theory is employed with the process-oriented FEA of FO-PLP to clarify the stress-free temperature of the equivalent RDL. An actual FO-PLP vehicle with Cu pillars is fabricated and measured to demonstrate the reliability of the proposed simulation methodology. An average deviation of less than 10% is obtained between the simulated prediction and experiments. The results of factorial design indicate that the mechanical properties of dielectrics and RDL are the dominant factors and have an interactive effect on the warpage magnitude of FO-PLP.

Warpage Estimation and Demonstration of Panel-Level Fan-Out Packaging With Cu Pillars Applied on a Highly Integrated Architecture

Die shift in fan-out wafer-level packaging (FOWLP) is a major roadblock, limiting package scaling and performance. It not only limits the wire pitch but also results in reliability problems and yield loss. In this work, we systematically investigate and predict the in-plane and out-of-plane die shift through numerical and experimental analysis in FlexTrate, which is a flexible hybrid electronics (FHE) platform based on FOWLP for flexible heterogeneous integration. First, the in-plane die shift is studied through simulation of the molding process and the substrate cure shrinkage. The molding process is simulated through a fluid analysis which explores the shear force. In addition, a thermo-mechanical analysis simulates the polydimethylsiloxane (PDMS) curing process followed by handler release. Based on this model, the effect of die size, die spacing, die thickness, and PDMS thickness on die shift are analyzed. The results indicate that smaller die size has a larger impact on die shift compared to the other factors. The predicted die shift is compared with the experimental results to verify the validity. Further, the experimental characterization of out-of-plane die shift is analyzed through the study of substrate warpage and die placement force which reveal the deleterious effect of high temperature processes. Finally, using the developed numerical model, the die placement is optimized for a surface electromyography (sEMG) system. This detailed analysis sheds light on the various factors which influence die shift, and hence is an important step to push the boundaries of current FHE to new limits.

Comprehensive Investigation of In-Plane and Out-of-Plane Die Shift in Flexible Fan-Out Wafer-Level Packaging Using Polydimethylsiloxane

This letter describes a direct Cu bonding technology to there-dimensionally integrate heterogeneous dielets based on a chip-on-wafer configuration. 100-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>-cubed blue <inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>LEDs temporarily adhered on a photosensitive resin are interconnected by semi-additive plating (SAP) without thermal compression bonding. By using SAP bonding, a lot of dielets can be stacked on thin 3D-IC chiplets. The following three key technologies are applied to solve the yield issues of SAP bonding. After pick-and-place assembly, additional coplanarity enhancement eliminates Cu bridges grown to a small gap between the <inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>LEDs and photosensitive resin. The <inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>LEDs arrays with sidewalls insulated by room-temperature ozone-ethylene-radical (OER)-SiO2-CVD are successfully bonded on sapphire wafers and a thin 3D-IC with through-Si via (TSV). Further design optimization is required, but partial seed pre-etching works well to increase the yield. Fully integrated module implementation with the 3D-ICs will be the next stage, however, we discuss a superior prospect for yield enhancement toward nearly 100%.

https://ieeexplore.ieee.org/ielx7/55/4357973/10021594.pdf

Typical die shift is beyond several tens micrometers or more, which is a serious problem on advanced fan-out wafer-level packaging (FOWLP), to give inevitable misalignment errors in the subsequent photolithography processes for fine-pitch redistributed wiring layer (RDL) formation. In particular, this problem is expected to grow all the more serious in chiplets and tiny dies less than 1 mm in a side. In this work, the use of an anchoring layer is proposed to fix these dies/chiplets on a double-side laminate thermo-release tape and drastically reduce the die shift. In addition, an on-nail photoplethysmogram (PPG) sensor module as a part of flexible hybrid electronics (FHE) is integrated with $\mu $ LED ( $270\,\,\mu \text{m}\,\,\times 270\,\,\mu \text{m}$ ) based on a die-first FOWLP methodology using a biocompatible polydimethylsiloxane (PDMS) mold resin for real-time monitoring pulse wave and percutaneous oxygen saturation (SpO2). The repeated bendability of fan-out Au wirings formed on the PDMS and the current–voltage ( $I$ – $V$ ) behavior of the $\mu $ LED before and after die embedment in the PDMS is characterized.

/pdf/significant-die-shift-reduction-and-m-led-integration-based-gkzv93fz54.pdf

Significant Die-Shift Reduction and μ LED Integration Based on Die-First Fan-Out Wafer-Level Packaging for Flexible Hybrid Electronics

This paper deals with a flexible 3D-IC system fabrication methodology. Mini-LEDs and 3D-IC chiplets divided from a large 3D-IC with Cu-TSVs are embedded in an elastomer PDMS based on die-first FOWLP for heterogeneously integrating them into Smart Skin Display as a biomedical/wearable FHE (flexible hybrid electronics). We address a serious die-shift issue for the tiny chips in die-first FOWLP by using a new anchoring layer technique to drastically reduce the shift within $2.7\ \mu\mathrm{m}$ including assembly positioning errors. The mechanical/electrical properties of the flexible array of 3D-IC chiplets are characterized before and after repeated bending with a curvature radius of 10 mm. In addition, stress neutral axes are designed to stably endure bending cycle applicable to the biomedical/wearable FHE with multi-level metallization.

FOWLP-Based Flexible Hybrid Electronics with 3D-IC Chiplets for Smart Skin Display

We have reported a new flexible hybrid electronics (FHE) whose structure is consisting of heterogeneous small/thin/rigid chiplets embedded in 2D molded polymeric substrates such as PDMS and hydrogel on which fine-pitch fanout RDLs are formed by die-first or RDL-first FOWLP. In this study, we apply this FHE methodology to flexible 3D In-Mold Electronics (IME) for highly integrated 3D electronics. 1-mm-square Si chiplets are embedded in PDMS and biocompatible Au RDLs are formed on the elastomer in die-first FOWLP processing, and finally, the resulting 2D FHE (2D-PDMS) is re-molded again to give contact lens-shaped flexible 3D IME (3D-PDMS). In addition, we design the flexible 3D interconnections with self-assembled corrugation of out-of-plane tortuousness by controlling a CTE mismatch between the Au layer and the underneath insulator of flexible epoxy formed on the PDMS.

Tomo Odashima

Papers

Significant Die-Shift Reduction and μ LED Integration Based on Die-First Fan-Out Wafer-Level Packaging for Flexible Hybrid Electronics

FOWLP-Based Flexible Hybrid Electronics with 3D-IC Chiplets for Smart Skin Display

Wafer-Level Flexible 3D Corrugated Interconnect Formation for Scalable In-Mold Electronics with Embedded Chiplets