T
Tony Givargis
Researcher at University of California, Irvine
Publications - 134
Citations - 3496
Tony Givargis is an academic researcher from University of California, Irvine. The author has contributed to research in topics: System on a chip & Cache. The author has an hindex of 29, co-authored 125 publications receiving 3289 citations. Previous affiliations of Tony Givargis include University of California, Berkeley & University of California.
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Embedded System Design: A Unified Hardware / Software Introduction
Frank Vahid,Tony Givargis +1 more
TL;DR: This paper presents a meta-modelling system that automates the very labor-intensive and therefore time-heavy and therefore expensive and expensive process engineering process, called a single-Purpose Processor, by simplifying the design process.
Journal ArticleDOI
A Survey on Concepts, Applications, and Challenges in Cyber-Physical Systems
TL;DR: An extensive set of technical challenges are enumerated and specific applications are used to elaborate and provide insight into each specific concept in the Cyber-Physical System.
Proceedings ArticleDOI
Multi-objective design space exploration using genetic algorithms
Maurizio Palesi,Tony Givargis +1 more
TL;DR: This work provides a technique for efficiently exploring a parameterized system-on-a-chip (SoC) architecture to find all Pareto-optimal configurations in a multi-objective design space and applies genetic algorithms (GAs) to discover Paringtonimal configurations within the remaining design points.
Journal ArticleDOI
Real-time differential carrier phase GPS-aided INS
TL;DR: The implementation achieves 100-Hz vehicle state estimates with position accuracies at the centimeter level through the use of differential carrier phase GPS techniques.
Journal ArticleDOI
Platune: a tuning framework for system-on-a-chip platforms
Tony Givargis,Frank Vahid +1 more
TL;DR: The power estimation techniques for processors, caches, memories, buses, and peripherals combined with the design space exploration algorithm deployed by Platune form a methodology for design-of tuning frameworks for parameterized SOC platforms in general.