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Showing papers by "Toru Takayama published in 1995"


Patent
24 May 1995
TL;DR: In this paper, a process for fabricating a thin-film transistor, which comprises crystallizing an amorphous silicon film, forming thereon a gate insulating film and a gate electrode, implanting impurities in a self-aligned manner, and annealing the resulting structure at a temperature lower than the deformation temperature of the substrate to activate the doped impurities.
Abstract: A process for fabricating a thin film transistor, which comprises crystallizing an amorphous silicon film, forming thereon a gate insulating film and a gate electrode, implanting impurities in a self-aligned manner, adhering a coating containing a catalyst element which accelerates the crystallization of the silicon film, and annealing the resulting structure at a temperature lower than the deformation temperature of the substrate to activate the doped impurities. Otherwise, the catalyst element can be incorporated into the structure by introducing it into the impurity region by means of ion implantation and the like. Also a process for fabricating a thin film transistor, which comprises forming a gate electrode, a gate insulating film, and an amorphous silicon film on a substrate, implanting impurities into the amorphous silicon film to form source and drain regions as the impurity regions, introducing a catalyst element into the impurity region by adhering a coating containing the catalyst element of by means of ion doping and the like, and annealing the resulting structure at a temperature lower than the deformation temperature of the substrate to activate the doped impurities.

141 citations


Patent
07 Jun 1995
TL;DR: In this article, a thin-film transistor is described, which includes a gate electrode, a gate insulating film, an amorphous silicon film having impurities implanted therein to form source and drain regions as impurity regions, and a catalyst element introduced into the impurity region by adhering a coating containing the catalyst element or by means of ion doping and the like.
Abstract: A thin film transistor includes a crystallized amorphous silicon film having a gate insulating film and a gate electrode formed thereon. The device includes impurities implanted in a self-aligned manner and a catalyst that accelerates the crystallization of the silicon film. The catalyst is introduced in the silicon film by adhering a coating containing the catalyst element and annealing the resulting structure at a temperature lower than the deformation temperature of the substrate to activate the doped impurities. The catalyst element can also be incorporated into the silicon film by means of ion implantation and the like. Also disclosed is a thin film transistor, which comprises a gate electrode, a gate insulating film, an amorphous silicon film having impurities implanted therein to form source and drain regions as the impurity regions, and a catalyst element introduced into the impurity regions by adhering a coating containing the catalyst element or by means of ion doping and the like, wherein the resulting structure is annealed at a temperature lower than the deformation temperature of the substrate to activate the doped impurities.

114 citations


Patent
13 Feb 1995
TL;DR: In this article, the amorphous silicon film is thermally annealed to crystallize it, and the surface of the obtained crystalline silicon film was etched to a depth of 20 to 200 Å, thus producing a clean surface.
Abstract: Method of fabricating a semiconductor device, such as a thin-film transistor, having improved characteristics and improved reliability. The method is initiated with formation of a thin amorphous silicon film on a substrate. A metallization layer containing at least one of nickel, iron, cobalt, and platinum is selectively formed on or under the amorphous silicon film so as to be in intimate contact with the silicon film, or these metal elements are added to the amorphous silicon film. The amorphous silicon film is thermally annealed to crystallize it. The surface of the obtained crystalline silicon film is etched to a depth of 20 to 200 Å, thus producing a clean surface. An insulating film is formed on the clean surface by CVD or physical vapor deposition. Gate electrodes are formed on the insulating film.

100 citations


Patent
12 May 1995
TL;DR: In this article, a semiconductor circuit having a plurality of crystalline thin-film transistors possessing different electrical characteristics which are formed on a substrate having an active matrix region and a driver circuit region is described.
Abstract: A semiconductor circuit having a plurality of crystalline thin film transistors possessing different electrical characteristics which are formed on a substrate having an active matrix region and a driver circuit region. At least one first thin film transistor comprising a first crystalline silicon film is formed on the active matrix region of the substrate, while at least one second thin film transistor comprising a second crystalline silicon film is formed on the driver circuit region. The crystalline film of each of the first thin film transistors contains a catalyst element capable of promoting the crystallization of silicon at a higher concentration than the crystalline film of each of the second thin film transistors.

91 citations


Patent
06 Jun 1995
TL;DR: In this paper, a small amount of a catalyst element for promoting crystallization is added to an amorphous silicon film, and an annealing process is conducted at a temperature which is lower than the distortion temperature of a substrate, thereby crystallizing the amorphized silicon film.
Abstract: A substance containing a catalyst element is formed so as to closely contact with an amorphous silicon film, or a catalyst element is introduced into the amorphous silicon film. The amorphous silicon film is annealed at a temperature which is lower than a crystallization temperature of usual amorphous silicon, thereby selectively crystallizing the amorphous silicon film. The crystallized region is used as a crystalline silicon TFT which can be used in a peripheral driver circuit of an active matrix circuit. The region which remains amorphous is used as an amorphous silicon TFT which can be used in a pixel circuit. A relatively small amount of a catalyst element for promoting crystallization is added to an amorphous silicon film, and an annealing process is conducted at a temperature which is lower than the distortion temperature of a substrate, thereby crystallizing the amorphous silicon film. A gate insulating film, and a gate electrode are then formed, and an impurity is implanted in a self-alignment manner. A film containing a catalyst element for promoting crystallization is closely contacted with the impurity region, or a relatively large amount of a catalyst element is introduced into the impurity region by an ion implantation or the like. Then, an annealing process is conducted at a temperature which is lower than the distortion temperature of the substrate, thereby activating the doping impurity.

18 citations


Patent
09 Dec 1995
TL;DR: In this article, a semiconductor film is placed and heated in a helium atmosphere, and the surface of the semiconductor is irradiated with a laser beam to reduce the time required for laser processing.
Abstract: PROBLEM TO BE SOLVED: To reduce time required for laser processing of semiconductor film. SOLUTION: A semiconductor film is placed and heated in a helium atmosphere. The surface of the semiconductor film is irradiated with a laser beam. As the helium atmosphere, helium alone, or a mixture of helium and hydrogen, helium and oxygen, or helium, hydrogen and oxygen, or a plasma of these elements are used. Since the thermal conductivity of helium is higher than that of other elements, the time required to heat the substrate in the helium atmosphere is shorter than in another gas such as air. COPYRIGHT: (C)1997,JPO

7 citations


Patent
28 Mar 1995
TL;DR: Amorphous silicon in impurity regions (source and drain regions or N-type or p-type regions) of TFT and TFD are crystallized and activated to lower electric resistance, by depositing film having a catalyst element such as nickel (Ni), iron (Fe), cobalt (Co) or platinum (Pt) on or beneath an amorphous silicon film.
Abstract: Amorphous silicon in impurity regions (source and drain regions or N-type or p-type regions) of TFT and TFD are crystallized and activated to lower electric resistance, by depositing film having a catalyst element such as nickel (Ni), iron (Fe), cobalt (Co) or platinum (Pt) on or beneath an amorphous silicon film, or introducing such a catalyst element into the amorphous silicon film by ion implantation and subsequently crystallizing the same by applying heat annealing at an appropriate temperature.

6 citations


Patent
28 Sep 1995
TL;DR: In this paper, a trace catalyst was added to an amorphous silicon film to accelerate the crystallization of the silicon film, which reduced the crystallizing temperature and shortened the crystallising time.
Abstract: PURPOSE: To improve the crystallizability of source and drain regions turned into amorphous by a method wherein a trace catalyst material is added to an amorphous silicon film to accelerate the crystallization of the silicon film, the crystallizing temperature of the silicon film is reduced and the crystallizing time of the silicon film is shortened. CONSTITUTION: A crystalline silicon active layer on an insulating surface layer 101 is constituted of a lightly doped impurity region 106 between a channel formation region 104 and source and drain regions 105 and 108 and a lightly doped region 107 between the source and drain regions 105 and 108 and the region 104. A gate insulating film 102 and a gate electrode 103 are formed on the active layer. An interlayer insulator film 109 is provided in such a way as to cover the electrode 103. Electrodes 110 and 111, which are respectively provided on the regions 105 and 108, are respectively formed in contact holes formed in the interlayer insulator film 109. A catalyst element is mainly introduced into the regions 105 and 108 and the concentration of the element is set at 1×10 7 atom/cm 2 or higher. Thereby, a crystallization of the regions 105 and 108 is accelerated and the crystallizability of the source and drain regions turned into amorphous is improved. COPYRIGHT: (C)1996,JPO

2 citations