Showing papers by "Toshitsugu Sakamoto published in 2022"

Via-switch FPGA with transistor-free programmability enabling energy-efficient near-memory parallel computation

Abstract: We are developing field-programmable gate arrays (FPGAs) with a new non-volatile switch called via-switch. In via-switch FPGAs (VS-FPGAs), the via-switches required for reconfiguration are placed in the routing layer so that the entire transistor layer can be utilized for computing, and higher implementation density can be achieved compared to conventional SRAM FPGAs. Furthermore, since arithmetic units and memories for computing can be placed under the via-switch crossbar for routing, large-scale parallel operations can be realized where the memory and the arithmetic unit are adjacent to each other. These features enable operation with high energy efficiency. This article reports 65 nm prototype fabrication results and predicted the performance of the VS-FPGA designed for AI applications. We also present the developed application mapping flow and crossbar programming method. The VS-FPGA closes the gap between FPGA and application-specific integrated circuits (ASIC) with the performance advantage of the via-switch and via-switch copy scheme for FPGA-to-ASIC migration, contributing to the expansion of the FPGA usage.

28nm Atom-Switch FPGA: Static Timing Analysis and Evaluation

Abstract: A static timing analysis (STA) tool for a 28nm atom-switch FPGA (AS-FPGA) is introduced to validate the signal delay of an application circuit before implementation. High accuracy of the STA tool is confirmed by implementing a practical application circuit on the 28nm AS-FPGA. Moreover, dramatic improvement of delay and power is demonstrated in comparison with a previous 40nm AS-FPGA.

Enhanced Drain Current in Transient Mode due to Long Ionization Time of Shallow Impurities at 4 K in 65-nm bulk Cryo CMOS Transistors

Abstract: Despite the importance of cryo CMOS technologies in quantum computing systems, the transient behaviors of cryo MOS transistors have been less studied. In this work, in advanced CMOS transistors we observed sub-us transient drain current $(I_{\mathrm{d}}^{\text{Trans}})$ that was much greater than the static drain current $(I_{\mathrm{d}}^{\text{Static}})$ at 4 K (Fig. 6); the transient-to-static ratio $r\equiv I_{\mathrm{d}}^{\text{Trans}}/I_{\mathrm{d}}^{\text{Static}}$ reached as large as 2.7 (Fig. 9), whereas $r$ stays at one in the same device at 20 K. The observed transient characteristics are not due to the self-heating effects, but due to the long emission time of holes from acceptors at 4 K. After applying biases, more electrons flow into the channel than those in static conditions to mitigate the frozen acceptors. $I_{\mathrm{d}}^{\text{Trans}}$. goes down to $I_{\mathrm{d}}^{\text{Static}}$ because of gradual ionization of acceptors. We consider that the observed transient behavior needs to be considered in cryo MOSFET model to accurately design cryo LSI circuits.