T
Tsukasa Shirotori
Researcher at Toshiba
Publications - 16
Citations - 814
Tsukasa Shirotori is an academic researcher from Toshiba. The author has contributed to research in topics: Sense amplifier & CPU cache. The author has an hindex of 9, co-authored 16 publications receiving 787 citations.
Papers
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Journal ArticleDOI
A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture
TL;DR: In this article, two new power-saving schemes for high-performance VLSIs with a large-scale memory and many interface signals are described, one is a current-controlled latch sense amplifier that reduces the power dissipation by stopping sense current automatically.
Journal Article
A Current-Controlled Latch Sense Amplifier and a Static Power-Saving Input Buffer for Low-Power Architecture
TL;DR: In this paper, two new power-saving schemes for high-performance VLSIs with a large-scale memory and many interface signals are described, one is a current-controlled latch sense amplifier that reduces the power dissipation by stopping sense current automatically.
Patent
Semiconductor integrated circuit capable of testing memory blocks
TL;DR: In this article, the authors propose a test mode for a plurality of writable/readable memory blocks with different address spaces and an address decoder for selecting addresses of the memory blocks.
Journal ArticleDOI
A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC
Kazutaka Nogami,Takayasu Sakurai,Kazuhiro Sawada,Kenji Sakaue,Yuichi Miyazawa,Sumio Tanaka,Yoichi Hiruta,K. Katoh,Toshinari Takayanagi,Tsukasa Shirotori,Y. Itoh,Masanori Uchida,Tetsuya Iizuka +12 more
TL;DR: A 32-kB cache macro with an experimental reduced instruction set computer (RISC) is realized and a pipelined cache access to realize a cycle time shorter than the cache access time is proposed.
Patent
Semiconductor memory device employing sense amplifier control circuit and word line control circuit
TL;DR: In this paper, a memory cell array, a plurality of address lines, a pair of data lines, an address transition detector circuit, a sense amplifier, sense amplifier control circuit for activating the sense amplifier in response to the address transition signal, and a word line control circuit which deactivates the word lines within the memory cell arrays.