Linear models

Digital technology works so well because at the heart of digital representation, there are only a few basic components. Nowadays, these basic components usually are binary digits, bits for short, called binary because they are designed to stand for only two different values, conveniently called zero and one. A stored or transmitted bit's state can deteriorate quite badly before a processing device will be mistaken in deciding which of the two possible values is the original.

Binary Arithmetic

The power efficiency of cellular base stations is a crucial element to maintain sustainability of future mobile networks. To investigate future network concepts, a good power model is required which is highly flexible to evaluate the diversity of power saving options. This paper presents an advanced power model which supports a broad range of network scenarios and base station types, features and configurations. In addition to the power consumption, the model also provides values on the hardware sleep capabilities (sleep depths, transition times, power savings). The paper also discusses the technology trends and scaling factors which are used to predict the power consumption of base stations up to the year 2020. Two use cases are described, illustrating the power savings over different sleep depths, and quantifying the power consumption evolution over different technology generations.

A Flexible and Future-Proof Power Model for Cellular Base Stations

Натрийуретические пептиды (НУП) являются важными биомаркерами в диагностике и определении прогноза у пациентов с сердечной недостаточностью (СН). Оценка динамики концентрации НУП (BNP, Nt -proBNP) может быть использована в качестве критерия успешности проводимой терапии. так, при достижении целевых уровней НУП можно прогнозировать благоприятный исход заболевания. В настоящее время лечение СН с учетом уровней НУП является частью рекомендаций по лечению СН (класс IIа) и улучшению ее исхода (класс IIб) в США, однако такой подход не используется в российских клиниках. Цель. Представить современный взгляд на возможность использования НУП для оценки эффективности проводимой терапии пациентов с СН. Ключевые слова: натрийуретические пептиды, сердечная недостаточность, оценка эффективности терапии.

Федеральное государственное бюджетное учреждение «Научно-исследовательский институт комплексных проблем сердечно-сосудистых заболеваний» Сибирского отделения Российской академии медицинских наук, Кемерово, Россия

The article analyzes the problem of energy efficient techniques in cooperative spectrum sensing (CSS). Although it was proven that single-device sensing is not sufficient for reliable sensing, cooperative spectrum sensing was proposed, burdened, however, with great overhead. Thus, work on the topic of energy efficient cooperative schemes gained more interest, which resulted in a number of energy efficient cooperative algorithm proposals. In this work, we try to classify the possible directions in energy efficient CSS and present a limited set of works introducing new ideas to an energy efficient CSS algorithm.

Energy-Efficient Cooperative Spectrum Sensing: A Survey

This paper presents a design methodology for power and area minimization of flexible FFT processors. The methodology is based on the power-area tradeoff space obtained by adjusting algorithm, architecture, and circuit variables. Radix factorization is the main technique for achieving high energy efficiency with flexibility, followed by architecture parallelism and delay line circuits. The flexibility is provided by reconfigurable processing units that support radix-2/4/8/16 factorizations. As a proof of concept, a 128- to 2048-point FFT processor for 3GPP-LTE standard has been implemented in a 65-nm CMOS process. The processor designed for minimum power-area product is integrated in 1.25 × 1.1 mm2 and dissipates 4.05 mW at 0.45 V for the 20 MHz LTE bandwidth. The energy dissipation ranging from 2.5 to 103.7 nJ/FFT for 128 to 2048 points makes it the lowest energy flexible FFT.

https://ir.nctu.edu.tw:443/bitstream/11536/15606/1/000300577500015.pdf

Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example

Spectrum sensing over a wide bandwidth increases the probability of finding unutilized spectrum for cognitive radios. The hardware realization of wideband sensing is challenging because strong primary users introduce large dynamic range and spectral leakage in adjacent unused bands. This paper proposes a multitap-windowed frequency power detector with adaptive threshold and sensing time to address the above challenges. The suppression of spectral leakage is achieved by multitap-windowed FFT processing, which also enables reduced sensing time. The sensing time and detection threshold are adapted according to the channel-specific spectral leakage, which results in a reliable wideband signal detection within constrained sensing time. Our simulations with a 20 dB interferer-to-noise ratio (INR) indicate a 2× improvement in detection rate compared to conventional power detectors. An order-of-magnitude improvement in sensing time is achieved in the presence of 30-dB INR interferers while maintaining a false-alarm rate of 0.1 and a detection rate of 0.9. The proposed algorithms are realized in an FPGA to demonstrate real-time operation with a latency below 10 μ s. Experimental results from a radio testbed closely match the numerical simulations. An ASIC architecture for a 200-MHz bandwidth is estimated to occupy 0.98 mm2 and dissipate 25 mW from a 1-V supply in a standard 65-nm CMOS technology.

A Wideband Spectrum-Sensing Processor With Adaptive Detection Threshold and Sensing Time

Following the rapid expansion of mobile computing in the past decade, mobile system-on-a-chip (SoC) designs have off-loaded most compute-intensive tasks to dedicated accelerators to improve energy efficiency. An increasing number of accelerators in power-limited SoCs results in large regions of “dark silicon.” Such accelerators lack flexibility, thus any design change requires a SoC re-spin, significantly impacting cost and timeline. To address the need for efficiency and flexibility, this work presents a multi-granularity FPGA suitable for mobile computing. Occupying 20.5mm2 in 40nm CMOS, the chip incorporates 2,760 fine-grained configurable logic blocks (CLBs) with 11,040 6-input look-up-tables (LUTs) for random logic, basic arithmetic, shift registers, and distributed memories, 42 medium-grained 48b DSP processors for MAC and SIMD operations, 16 32K×1b to 512×72b reconfigurable block RAMs, and 2 coarsegrained kernels: a 64-8192-point fast Fourier transform (FFT) processor and a 16-core universal DSP (UDSP) for software-defined radio (SDR). Using a mixradix hierarchical interconnect, the chip achieves a 4× interconnect area reduction over commercial FPGAs for comparable connectivity, reducing overall area and leakage by 2.5×, and delivering a 10-50% lower active power. With coarse-grained kernels, the chip's energy efficiency reaches within 4-5× of ASIC designs.

27.5 A multi-granularity FPGA with hierarchical interconnects for efficient and flexible mobile computing

A common technique for cognitive radio wideband spectrum sensing is energy/power detection of primary users (PU) in frequency domain. Specifically, power spectrum estimation methods are combined with power detection statistics to test the PU presence. However, when detecting in a particular band of interest these techniques suffer from energy leakage and adjacent channel interference. In this paper, we derive a common matrix framework for the analytical performance of power detectors when FFT, windowed FFT, or multitap windowed FFT are used. Our matrix model is verified by simulations of modulated PU signals. We further propose a low-complexity compensation method to adapt the thresholds in the presence of large power difference between channels. By using both the multitap windowing and the constant false-alarm-rate method in the presence of strong signals, we demonstrate a 2-times increase in the detection rate performance as compared to existing methods. The proposed algorithm achieves similar PFA and PD as FFT at lower sample complexity, leading to reduced sensing times.

Cognitive Radio Wideband Spectrum Sensing Using Multitap Windowing and Power Detection with Threshold Adaptation

A digital baseband cognitive radio spectrum sensing processor with 200-kHz resolution over 200-MHz bandwidth is integrated in 1.64 mm2 in 65-nm CMOS. The processor uses adaptive channel-specific threshold and sensing time to achieve detection probability ≥ 0.9 and false-alarm probability ≤ 0.1 for -5-dB SNR and adjacent-band interferers of 30-dB INR within a 50-ms sensing time. The chip power and area are minimized by jointly considering algorithm, architecture, and circuit parameters. The chip dissipates 7.4 mW for a 200-MHz sensing bandwidth, which is a 22× reduction in power per sensing bandwidth compared with prior work.

https://ir.nctu.edu.tw:443/bitstream/11536/16711/1/000308007900024.pdf

Tsung-Han Yu

Papers

Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example

A Wideband Spectrum-Sensing Processor With Adaptive Detection Threshold and Sensing Time

27.5 A multi-granularity FPGA with hierarchical interconnects for efficient and flexible mobile computing

Cognitive Radio Wideband Spectrum Sensing Using Multitap Windowing and Power Detection with Threshold Adaptation

A 7.4-mW 200-MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios