Technology scaling has resulted in smaller and faster transistors in successive technology generations. However, transistor power consumption no longer scales commensurately with integration density and, consequently, it is projected that in future technology nodes it will only be possible to simultaneously power on a fraction of cores on a multi-core chip in order to stay within the power budget. The part of the chip that is powered off is referred to as dark silicon and brings new challenges as well as opportunities for the design community, particularly in the context of the interaction of dark silicon with thermal, reliability and variability concerns. In this perspectives paper we describe these new challenges and opportunities, and provide preliminary experimental evidence in their support.

The EDA Challenges in the Dark Silicon Era: Temperature, Reliability, and Variability Perspectives

3-D sequential integration stands out from other 3-D schemes as it enables the full use of the third dimension. Indeed, in this approach, 3-D contact density matches with the transistor scale. In this paper, we report on the main advances enabling the demonstration of functional and performant stacked CMOS-FETs; i.e., wafer bonding, low temperature processes (<;650°C) and salicide stabilization achievements. This integration scheme enables fine grain partitioning and thus a gain in performance versus cost ratio linked to separation of heterogeneous technologies on distinct levels. In this work, we will detail examples taking advantage of the unique 3-D contact pitch achieved with sequential 3-D.

3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS

Severe security threats and alerts associated with the use of smart devices have drawn increasing public attentions since the inception of Internet of Things (IoT) in late 1990s. IoT devices pose a unique and challenging scenario for hardware security because of their ubiquity and area-power cost constraints. Traditional software techniques and established cryptographic methods are either inadequate or impractical due to the computational capacity and permanent storage required to process and maintain the privacy of the secret key. In this light, Physical Unclonable Function (PUF), a burgeoning technology rooted in 2002, comes in handy as an inexpensive and yet effective security primitive to overcome the forgery tagging problem by its radically different way of generating and processing secret keys in security hardware. PUFs are hardware structures or functions designed to utilize the physical disorder of random nanoscale phenomena for the derivation of keys without having to keep any security-critical information explicitly in hardware. As we usher PUF into its 15th anniversary in 2017, it is timely to review the advancements of PUF over the past decade. Specifically, this survey addresses three fundamental questions which are at all times relevant in the security arms race. These questions are: how secure can a PUF be? what differences have PUFs brought to security applications and how do these differences impact existing security protocols? how is hardware implementation research influenced by the opportunities of nanotechnologies and new discoveries of disorder-based physical phenomena? It is hoped that this retrospective study of problems and solutions encountered in the journey of developing PUF to its current state will foreshadow the challenges and opportunities for future sustainable activities in the field.

A Retrospective and a Look Forward: Fifteen Years of Physical Unclonable Function Advancement

Innovations in relevant micro-contact areas are highlighted, these include, design, contact resistance modeling, contact materials, performance and reliability. For each area the basic theory and relevant innovations are explored. A brief comparison of actuation methods is provided to show why electrostatic actuation is most commonly used by radio frequency microelectromechanical systems designers. An examination of the important characteristics of the contact interface such as modeling and material choice is discussed. Micro-contact resistance models based on plastic, elastic-plastic and elastic deformations are reviewed. Much of the modeling for metal contact micro-switches centers around contact area and surface roughness. Surface roughness and its effect on contact area is stressed when considering micro-contact resistance modeling. Finite element models and various approaches for describing surface roughness are compared. Different contact materials to include gold, gold alloys, carbon nanotubes, composite gold-carbon nanotubes, ruthenium, ruthenium oxide, as well as tungsten have been shown to enhance contact performance and reliability with distinct trade offs for each. Finally, a review of physical and electrical failure modes witnessed by researchers are detailed and examined.

/pdf/a-review-of-micro-contact-physics-for-microelectromechanical-4z1vzxhmv2.pdf

A review of micro-contact physics for microelectromechanical systems (MEMS) metal contact switches

Hardware Trojans (HTs) pose a significant threat to the modern and pending integrated circuit (IC). Due to the diversity of HTs and intrinsic process variation (PV) in IC design, detecting and locating HTs is challenging. Several approaches have been proposed to address the problem, but they are either incapable of detecting various types of HTs or unable to handle very large circuits. We have developed a scalable HT detection and diagnosis approach that uses segmentation and gate level characterization (GLC). We ensure the detection of arbitrary malicious circuitry by measuring the overall leakage current for a set of different input vectors. In order to address the scalability issue, we employ a segmentation method that divides the large circuit into small sub-circuits using input vector selection. We develop a segment selection model in terms of properties of segments and their effects on GLC accuracy. The model parameters are calibrated by sampled data from the GLC process. Based on the selected segments we are able to detect and diagnose HTs by tracing gate level leakage power. We evaluate our approach on several ISCAS85/ISCAS89/ITC99 benchmarks. The simulation results show that our approach is capable of detecting and diagnosing HTs accurately on large circuits.

/pdf/scalable-hardware-trojan-diagnosis-4c23f5zeem.pdf

Scalable Hardware Trojan Diagnosis

Operation in the subthreshold region most often is synonymous to minimum-energy operation. Yet, the penalty in performance is huge. In this paper, we explore how design in the moderate inversion region helps to recover some of that lost performance, while staying quite close to the minimum-energy point. An energy-delay modeling framework that extends over the weak, moderate, and strong inversion regions is developed. The impact of activity and design parameters such as supply voltage and transistor sizing on the energy and performance in this operational region is derived. The quantitative benefits of operating in near-threshold region are established using some simple examples. The paper shows that a 20% increase in energy from the minimum-energy point gives back ten times in performance. Based on these observations, a pass-transistor based logic family that excels in this operational region is introduced. The logic family operates most of its logic in the above-threshold mode (using low-threshold transistors), yet containing leakage to only those in subthreshold. Operation below minimum-energy point of CMOS is demonstrated. In leakage-dominated ultralow-power designs, time-multiplexing will be shown to yield not only area, but also energy reduction due to lower leakage. Finally, the paper demonstrates the use of ultralow-power design techniques in chip synthesis.

/pdf/ultralow-power-design-in-near-threshold-region-37ua2hp61u.pdf

Ultralow-Power Design in Near-Threshold Region

This work presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay circuits designed on these test chips illustrate a range of important functions necessary for the implementation of integrated VLSI systems and lend insight into circuit design techniques optimized for the physical properties of these devices. To explore these techniques a hybrid electro-mechanical model of the relays' electrical and mechanical characteristics has been developed, correlated to measurements, and then also applied to predict MEM relay performance if the technology were scaled to a 90 nm technology node. A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area.

Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications

Following the rapid expansion of mobile computing in the past decade, mobile system-on-a-chip (SoC) designs have off-loaded most compute-intensive tasks to dedicated accelerators to improve energy efficiency. An increasing number of accelerators in power-limited SoCs results in large regions of “dark silicon.” Such accelerators lack flexibility, thus any design change requires a SoC re-spin, significantly impacting cost and timeline. To address the need for efficiency and flexibility, this work presents a multi-granularity FPGA suitable for mobile computing. Occupying 20.5mm2 in 40nm CMOS, the chip incorporates 2,760 fine-grained configurable logic blocks (CLBs) with 11,040 6-input look-up-tables (LUTs) for random logic, basic arithmetic, shift registers, and distributed memories, 42 medium-grained 48b DSP processors for MAC and SIMD operations, 16 32K×1b to 512×72b reconfigurable block RAMs, and 2 coarsegrained kernels: a 64-8192-point fast Fourier transform (FFT) processor and a 16-core universal DSP (UDSP) for software-defined radio (SDR). Using a mixradix hierarchical interconnect, the chip achieves a 4× interconnect area reduction over commercial FPGAs for comparable connectivity, reducing overall area and leakage by 2.5×, and delivering a 10-50% lower active power. With coarse-grained kernels, the chip's energy efficiency reaches within 4-5× of ASIC designs.

27.5 A multi-granularity FPGA with hierarchical interconnects for efficient and flexible mobile computing

This paper presents an automated tool for floating-point to fixed-point conversion. The tool is
based on previous work that was built in MATLAB/Simulink environment and Xilinx System
Generator support. The tool is now extended to include Synplify DSP blocksets in a seamless
way from the users' view point. In addition to FPGA area estimation, the tool now also includes
ASIC area estimation for end-users who choose the ASIC flow. The tool minimizes hardware cost
subject to mean-squared quantization error (MSE) constraints. To obtain more accurate ASIC
area estimations with synthesized results, 3 performance levels are available to choose from,
suitable for high-performance, typical, or low-power applications. The use of the tool is first
illustrated on an FIR filter to achieve over 50% area savings for MSE specification of 10−6 as compared to all 16-bit realization. More complex optimization results for chip-level designs are also demonstrated.

/pdf/an-automated-fixed-point-optimization-tool-in-matlab-xsg-3qgi45yo9v.pdf

An Automated Fixed-Point Optimization Tool in MATLAB XSG/SynDSP Environment

A 2048 look-up-table FPGA with a radix-2 hierarchical interconnect network is realized in 3.94mm2 in 65-nm CMOS. It has an interconnect-to-logic area ratio of 1:1, which is a 3–4x reduction from modern FPGAs while allowing up to 100% resource utilization. As a proof of concept, it is designed with standard cells, achieving 16.4 GOPS/mm2 at 370MHz. Peak energy efficiency of 1.1 GOPS/mW is measured at 0.5V.

Cheng C. Wang

Papers

Ultralow-Power Design in Near-Threshold Region

Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications

27.5 A multi-granularity FPGA with hierarchical interconnects for efficient and flexible mobile computing

An Automated Fixed-Point Optimization Tool in MATLAB XSG/SynDSP Environment

A 1.1 GOPS/mW FPGA chip with hierarchical interconnect fabric